Intel Corporation

Seiichi Morimoto

Robert P Meagley

Mansour Moinpour

Reza M Golzarian

Robert J Patterson

Mark T Bohr

Uday Shah

Ebrahim Andideh

Joseph M Steigerwald

Peter K Moon

Nancy M Zelick

Lawrence N Brigham

Timothy L Deeter

Spencer E Preston

Wayne A Mattingly

Techniques are disclosed for fabricating FinFET transistors (e.g., double-gate, trigate, etc). A sacrificial gate material (such as polysilicon or other suitable material) is deposited on fin structure, and polished to remove topography in the sacrificial gate material layer prior to gate patterning. A flat, topography-free surface (e.g., flatness of 50 nm or better, depending on size of minimum feature being formed) enables subsequent gate patterning and sacrificial gate material opening (via polishing) in a FinFET process flow. Use of the techniques described herein may manifest in structural ways. For instance, a top gate surface is relatively flat (e.g., flatness of 5 to 50 nm, depending on minimum gate height or other minimum feature size) as the gate travels over the fin. Also, a top down inspection of gate lines will generally show no or minimal line edge deviation or perturbation as the line runs over a fin.

Polish to remove topography in sacrificial gate layer prior to gate patterning

A method of forming and a device including an interconnect structure having a unidirectional electrical conductive material is described. The unidirectional conductive material may overlie interconnect materials, and/or may surround interconnect materials, such as by lining the walls and base of a trench and via. The unidirectional conductive material may be configured to conduct electricity in a direction corresponding to a projection to or from a contact point and conductive material overlying the unidirectional conductive material, but have no substantial electrical conductivity in other directions. Moreover, the unidirectional conductive material may be electrically conductive in a direction normal to a surface over which it is formed or in directions along or across a plane, but have no substantial electrical conductivity in other directions. Finally, the unidirectional conductive material may have properties tending to reduce metal diffusion, reduce electron migration, provide adhesion or bonding, and/or act as an etch stop.

Unidirectionally conductive materials for interconnection

A method for optimally sizing dummy structures in an integrated circuit design is disclosed. Adjacent dummy structures are merged to provide a composite merged dummy structure. Each side of a first dummy structure representation is expanded in a lateral direction by a predetermined distance such that the first dummy structure representation merges with an adjacent second dummy structure representation forming the composite merged dummy structure. The composite merged dummy structure is then examined to determine if it exceeds a predetermined size. If the composite merged dummy structure exceeds the predetermined size, then the composite merged dummy structure is contracted to fit within predetermined perimeters.

Merging dummy structure representations for improved distribution of

A polishing process for polysilicon gate patterning improvement using standard patterning techniques in the manufacture of high performance metal oxide semiconductor (MOS) devices. The addition of a short silicon polish step, after deposition and before patterning of a polysilicon layer reduces the non-planarity normally associated with polysilicon. Polysilicon polishing removes the surface roughness in the polysilicon layer caused by the grain structure of polysilicon and the surface roughness due to the replication of the underlying topography of the isolation and substrate regions. The described method for removal of both types of surface roughness leaves the polysilicon layer planarized without increasing the defect level already associated with the manufacture of high performance MOS devices.

Polysilicon polish for patterning improvement

A method and apparatus for polishing a film formed over a semiconductor substrate. The substrate is pressed up against an abrasive pad so that the film contacts the pad. The pad has a diameter which is less than approximately two times a diameter of the substrate. While pressure is applied to the back of the substrate, the pad is rotated with respect to the wafer and an abrasive ceria slurry is introduced onto the pad to polish the film.

Elimination of pad conditioning in a chemical mechanical polishing

An improved method for planarizing the surface of an dielectric deposited over a semiconductor substrate. The substrate is pressed face down against a table which has been coated with an abrasive material. In this way, the upper surface of the interlayer dielectric contacts the abrasive. Rotational movement of the wafer relative to the table facilitates removal of the protruding portions of the interlayer dielectric by the abrasive. Post-planarization step height variation is minimized by simultaneously cooling the table and the abrasive material during the abrasive or polishing process. By maintaining the table and the abrasive at about 10 degrees Celcius the step height variation is reduced by a factor of 2 over that normally realized in the prior art.

Apparatus for planarizing a dielectric formed over a semiconductor

An improved method for planarizing the surface of an dielectric deposited over a semiconductor substrate. The substrate is pressed face down against a table which has been coated with an abrasive material. In this way, the upper surface of the interlayer dielectric contacts the abrasive. Rotational movement of the wafer relative to the table facilitates removal of the protruding portions of the interlayer dielectric by the abrasive. Post-planarization step height variation is minimized by simultaneously cooling the table and the abrasive material during the abrasive or polishing process. By maintaining the table and the abrasive at about 10 degrees Celsius the step height variation is reduced by a factor of 2 over that normally realized in the prior art.

Method of planarizing a dielectric formed over a semiconductor substrate

An improved method for conditioning the surface of a pad for polishing a dielectric layer formed on a semiconductor substrate is disclosed. In one embodiment, the serrated edge of an elongated blade member is first placed in radial contact with the surface of the polishing pad. The table and the pad are then rotated relative to the blade member. At the same time, the blade member is pressed downwardly against the pad surface such that the serrated edge cuts a plurality of substantially circumferential grooves into the pad surface. These grooves are dimensioned so as to facilitate the polishing process by creating point contacts which increases the pad area and allows more slurry to applied to the substrate per unit area. Depending on the type of pad employed, the number of teeth per inch on the serrated edge, the type of slurry used, etc., the downward force applied to the blade member in the rotational speed of the table are optimized to obtain the resultant polishing rate and uniformity desired.

Method for conditioning the surface of a polishing pad

Planarization process for planarizing glass layer which receives first layer metal. Spin-on-glass is cured in steam and then etched back using hydrofluoric and nitric acids diluted in acetic acids.

Growing community of inventors

Beaverton, OR, United States of America

Seiichi Morimoto