Hitachi, Ltd.

Hitachi Denshi Kabushiki Kaisha

Hitachi Global Storage Technologies Japan, Ltd.

Hitachi Medical Corporation

Hitachi Video Engineering, Incorporated

Hitachi Video and Information System, Inc.

N.v. Philips' Gloeilampenfabrieken

Other

U.S. Philips Corporation

Hitachi Global Storage Technologies Netherlands B.v.

Hatachi Ltd

Hitachi Video Eng. Inc.

Seiichi Mita

Morishi Izumita

Terumi Takashi

Nobukazu Doi

Naoki Satoh

Akihiko Hirano

Toshimitsu Kaku

Yoshiju Watanabe

Atsushi Saito

Hiroshi Ide

Yoshizumi Eto

Takeshi Maeda

Kazuo Shigematsu

Hideki Sawaguchi

Fumiyoshi Kirino

Hiroyuki Tsuchinaga

Tsuyoshi Toda

Masaharu Kondo

Yasuhide Ouchi

Masuo Umemoto

Morito Rokuda

Shoichi Miyazawa

Takushi Nishiya

Naoya Kobayashi

Hidehiro Kanada

Yasutaka Nishida

Shusaku Nagahara

Johannes W Bergmans

Fumio Kugiya

Takashi Nara

Ryushi Shimokawa

Hiroto Yamauchi

Mamoru Kaneko

Shigeru Nakamura

Hisataka Sugiyama

Eisaku Saiki

Masuo Kasai

Akira Saito

Toru Kawashima

Shigeyuki Ikeda

Yosuke Hori

Shintaro Suzumura

Kazutoshi Ashikawa

Toshihiro Nitta

Tsuguyoshi Hirooka

Hideki Miyasaka

Koji Shida

Yoichi Uehara

Hitoshi Katayama

Tomoaki Hirai

Fumio Hara

Satoshi Minoshima

Tetsuya Amano

Takashi Moriyasu

Motoyasu Terao

Hiroshi Kimura

Hiroshi Kuroda

Kazuhiro Sato

Takatoshi Kato

Yoshito Tsunoda

Yoshinori Okada

Toshiyuki Akiyama

Masahiro Ojima

Hisashi Nakamura

Tatsuya Hirai

Takeshi Nakao

Kenji Takahashi

Yoshinori Miyamura

Kiyoshi Matsumoto

Yoshihiro Hamakawa

Akihiko Kougami

Nobuo Murata

Hiroshi Yasuoka

Eiichi Seya

Hideki Imai

Yasuhiro Hirano

Yoshiteru Ishida

Hideyuki Yamakawa

Kazuyuki Takeshita

Yuichi Michikawa

Masanori Matsuzaki

Yasuo Inagaki

Susumu Kasai

Hiroyuki Hanyu

Shoichi Miyazawa, Deceased

Hideaki Maeda

Tsuyashi Toda

Horishi Ide

Kazutosi Ashikawa

Toru Kirino

Hitoshi Takagi

Hiroshi Shiono

Yuuichi Michikawa

Masuo Umenoto

Fuyuki Inui

Shigeaki Fujino

Kyoko Tsukano

In a data recovery processing, the conventional overhead, primarily, latency due to a rotational recording media is removed. Secondary, in a signal processing or in a recording and reproducing apparatus, reliability of data reproduction is improved by repeatedly processing data. These processing are achieved that input signal, i.e., raw analog signal read from the recording media is digitized to be stored in a secondary storage such as a memory or a FIFO memory. The apparatus includes a signal processing circuit to repeatedly process the stored digital signal in the secondary storage. When detecting data, operation of the circuit is efficiently controlled by a change over detector parameters, in which characteristics for the detecting performance. Resultantly, data recovery processing speed is increased and reliability of data reproduced is improved.

Signal processing apparatus and a data recording and reproducing apparatus including local memory processor

In one embodiment, a symbol error correction encoder effects block interleaving on recording data and thereafter performs first error correction encoding on the recording data. Next, a symbol error correction encoder performs encoding on the whole block. A reproducing processing circuit outputs likelihood information of respective bits. A first error correction decoder corrects a random error produced upon recording and reproduction, using the likelihood information. Since it is possible to make an improvement in performance with respect to the random error by repetitive decoding at this time, the post-correction data is returned to the reproducing processing circuit. After the completion of such repetitive processing, the data is digitized and subjected to an error correction in symbol unit by a hard determination, and outputted to a symbol error correction decoder.

Signal processing method and signal processing circuit

In a coding method which does not restrict a run length of '1' while data is recorded/reproduced, there are such a drawback that when an error correction is carried out, a total number of error data to be corrected is increased, and also errors of not-detectable data are increased. While data is coded, a continuous number of '1' contained in a code word is limited, and then an error correction is carried out inside a coding/decoding process operation. Thus, a recording/reproducing apparatus having a small number of decoding errors is available.

Decoding apparatus and decoding method

In a data demodulating method, predetermined input data is demodulated based upon a response characteristic of the partial response class 4; the demodulated input data is discrete-filtered to thereby produce filtering data; and the filtering data is maximum likelihood-decoded to thereby produce asymmetrical response data. Further, a magnetic recording/reproducing apparatus is arranged by using this data demodulating method.

Signal processing circuit

A digital magnetic recording/reproducing apparatus includes an LVA (List Viterbi Algorithm) detector which produces first to nth best sequences (n&#x3e;1) of a decoded result, and replaces a likelihood ratio and a path memory of the ith best sequence (i=2, 3, . . . , n) with those of the (2i&#x2212;1)th best sequence when contents of path memories of the (i&#x2212;1)th and ith best sequences are equal to each other and an absolute value of a difference between likelihood ratios of the (i&#x2212;1)th and (2i&#x2212;1)th best sequences is smaller than a decision threshold. Alternatively, the LVA detector initializes a likelihood ratio of the ith best sequence to be a likelihood ratio of the (i&#x2212;1)th best sequence with a constant difference value added thereto when contents of path memories of the (i&#x2212;1)th and ith best sequences are equal to each other.

Digital magnetic recording/reproducing apparatus

A signal processing apparatus capable of reducing burst error generation, and a highly reliable data recording/reproducing apparatus using this signal processing apparatus. This signal processing apparatus has a simple error detection/correction circuit provided just before a modulated code demodulator, thereby correcting error of a pattern easy to occur in a maximum likelihood decoder. The simple error detection/correction circuit is an error detection/correction circuit using a linear error correction code, for example, an error correction code (CRCC) formed of a cyclic code. Thus the number of burst errors after the modulated code demodulator can be decreased.

Signal processing apparatus and method, and data recording/reproducing apparatus using the same

Here is disclosed an information recording and reproducing apparatus comprising a multi-phase quadrature angular modulator for subjecting a signal to be written on a recording medium to multi-phase quadrature angular modulation to generate a modulated signal expressing information in phase difference and frequency difference, a quantizer for generating a discrete signal by making discrete the amplitude of the modulated signal generated by the quadrature angular modulator with reference to a certain level, a write head for writing the output signal of the quantizer onto the recording medium, a read head for reading information written on the recording medium, a read compensate circuit for compensating the phase and amplitude of a signal readout of the read head, and a multi-phase quadrature angular demodulator for demodulating a signal supplied from the read compensate circuit by subjecting it to multi-phase quadrature angular demodulation. By expressing information to be recorded in phase difference or frequency difference, it is made possible to record or reproduce the information at the varying timing of amplitude, and the bit inversion interval can be controlled by regulating the timing of amplitude variation.

Information recording and reproducing apparatus

A maximum likelihood decoding circuit is arranged to reduce the power consumption through the effect of the Viterbi algorithm. A plurality of storing elements to located vertically in a column and for storing each state survivor path information at the same time point are treated as storing element blocks ( ) to (D) in a manner to correspond to the combination (state) of intra-code interferences. The outputs from the storing elements to are again applied into the inputs of the corresponding storing elements contained in the same storing element block through the path history selecting circuits to . Each of the storing element block ( ) to (D) is periodically started on the input timing of a receiving signal at each processing time point by starting points (pointers) ( ) to (D) outputted from a starting signal (pointer) generating circuit . A storing element block output circuit and storing element block output terminals ( ) to (D) are provided in each of the storing element blocks ( ) to (D) so that a path memory circuit output may be outputted through an OR circuit

Decoding circuit using path sequence including feed-back type path sequence storing blocks

In a coding method which does not restrict a run length of &ldquo;1&rdquo; while data is recorded/reproduced, there are such a drawback that when an error correction is carried out, a total number of error data to be corrected is increased, and also errors of not-detectable data are increased. While data is coded, a continuous number of &ldquo;1&rdquo; contained in a code word is limited, and then an error correction is carried out inside a coding/decoding process operation. Thus, a recording/reproducing apparatus having a small number of decoding errors is available.

A signal processing circuit for a magnetic recording/reproducing apparatus, including at least an AGC, a PLL, a LPF, an equalizer circuit and a detection circuit, wherein a coefficient compensation circuit is formed by defining a constitution of the equalizer circuit, an error detection circuit is provided which operates by receiving input from the detection circuit, and the LSI is formed by a plurality of analog and digital chips, and the analog and digital chips are connected by current-output type D/A converters connected to at least the AGC and the PLL.

Signal processing circuit and information recording/reproducing apparatus using the same, and method for optimizing coefficients of equalizer circuit

A magnetic disk drive having an active filter supplied with a read waveform of a magnetic disk, an A/D converter supplied with an output of the active filter, a waveform equalizer supplied with an output of the A/D converter. An adaptive learning unit for adaptively learning a boost characteristic of the active filter on the basis of an input and an output of the waveform equalizer so that error in the waveform equalizer is minimized. An abnormal learning detection unit for detecting an abnormal operation in adaptive learning of the boost characteristic just after learning of a sector and a boost characteristic resetter for resetting the boost characteristic before adaptive learning to an initial value before adaptive learning of a next sector when abnormality occurs in adaptive learning of the adaptive learning unit.

Magnetic disk drive

There is provided a magnetic disk drive in which the adaptability of read signal processing of the magnetic disk drive is enhanced so that the frequency of retry or miscorrection in use is reduced. This magnetic disk drive has a read circuit, and a channel condition measuring circuit. An output of an A/D converter contained in the read circuit is supplied to a digital equalizing circuit so as to be equalized accurately. Upon input of a signal for instructing a coefficient learning circuit to learn the coefficient of the digital equalizing circuit, the initial coefficient registered in a register is set as a coefficient value in another register and the coefficient learning circuit is operated to start consecutive learning of coefficient values. In the channel condition measuring circuit, errors in a row of output values of the digital equalizing circuit are calculated and an integrated value of squares of the errors is compared with an error threshold value. If the integrated value is larger than the error threshold value, coefficient learning is regarded as being abnormal and a control signal for discarding the coefficient registered in the register is issued so that the register is reset to the initial coefficient value. The signal for instructing the coefficient learning circuit to learn the coefficient may be outputted in a sector previous to the read target sector or may be outputted in the read target sector.

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Kanagawa-ken, Japan

Seiichi Mita