Micron Technology Incorporated

Ps4 Luxco S.a.r.l.

Seiichi Maruno

Chiaki Dono

Chikara Kondo

Taihei Shido

Toshio Ninomiya

Seiji Narui

An apparatus includes a first external terminal, a first circuit, a signal line and a second circuit. The first external terminal receives at least one of data mask information and data bus inversion information. The first circuit performs one of an error check operation and a data bus inversion operation. The signal line is coupled between the first external terminal and the first circuit. The second circuit is coupled to the signal line and first a voltage level of the signal line at a substantially constant level responsive to a first control signal.

Apparatuses and methods for fixing a logic level of an internal signal line

A control circuit receives the mode signals supplied from a mode register and a read enable signal READ supplied from a control logic circuit, which activates enable signals ENto ENbased on the mode signals and read enable signal. For example, the read enable signal READ is activated when a read command is issued from the controller. One mode signal can indicate an operation mode in which a multi-purpose register is used, and another mode signal can indicate an operation mode in which the data bus inversion function is used. When a data masking operation is disabled and an error check operation is enabled, the mode register activates a protection signal SEL. When the data masking operation is enabled or the error check operation is disabled, the protection signal SEL is deactivated. The operation of a deserializer is controlled by clock signals and the protection signal SEL.

Disclosed herein is a device that includes an input receiver circuit activated by a strobe signal to generate an output signal by comparing a potential of an input signal with a reference potential, and a noise canceller cancelling noise superimposed on the reference potential due to a change in the strobe signal.

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Tokyo, Japan

Seiichi Maruno