Other

Hitachi, Ltd.

Renesas Technology Corp.

Hitachi Ulsi Systems Co., Ltd.

Hitachi Microcomputer Engineering, Ltd.

Hitachi Microcomputer System, Ltd.

Seiichi Ichihara

Ryosuke Kimoto

Ryo Haruta

Hiroshi Koyama

Hisao Nakamura

Shinji Tojo

Shinya Kanamitsu

Hiroshi Kawakubo

Noriyuki Takahashi

Chuichi Miyazaki

Ken Uchida

Tatsuo Itagaki

Hideo Meguro

Tsuneo Satoh

Yoshiaki Yoshiura

Koichi Nagasawa

Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.

Method of manufacturing a semiconductor device

In a semiconductor device manufacturing method in which a package including a semiconductor chip is mounted on a wiring board via tape ball grid array (TBGA), a tape base material having a device hole and a plurality of leads is provided with one end of the leads extended inside the device hole and a part of the other end of the leads forming lands for connecting bump electrodes. The semiconductor chip is arranged in the device hole of the tape base material to electrically connect the semiconductor chip and the one end of the leads. A sealing resin and reinforcing frame surrounding the periphery of the sealing resin are monolithically formed by transfer molding. The tape base material is fixed in an area between the semiconductor chip and the reinforcing frame by a lower mold and a projection of an upper mold.

Method of manufacturing a semiconductor device by monolithically forming a sealing resin for sealing a chip and a reinforcing frame by transfer molding

The thickness of a tape carrier package having a semiconductor chip is made uniform where bonding pads are concentrated on one side of the semiconductor chip. The tape carrier package is such that dummy pads are arranged on one side opposite to the side on which bonding pads (effective pins) are arranged in the semiconductor chip. Dummy leads are formed on an insulating tape The semiconductor chip is supported with inner lead portions connected to the corresponding bonding pads and the inner lead portions of the dummy leads connected to the corresponding dummy pads

Semiconductor device and process for producing the same

The thickness of a tape carrier package having a semiconductor chip is made uniform where bonding pads are concentrated on one side of the semiconductor chip. The tape carrier package is such that dummy pads,are arranged on one side opposite to the side on which bonding pads (effective pins),are arranged in the semiconductor chip. Dummy leads,are formed on an insulating tape,The semiconductor chip is supported with inner lead portions,connected to the corresponding bonding pads,and the inner lead portions,of the dummy leads,connected to the corresponding dummy pads

The thickness of a tape carrier package having a semiconductor chip is made uniform where bonding pads are concentrated on one side of the semiconductor chip. The tape carrier package is such that dummy pads 6b are arranged on one side opposite to the side on which bonding pads (effective pins) 6a are arranged in the semiconductor chip. Dummy leads 5 are formed on an insulating tape 4. The semiconductor chip is supported with inner lead portions 5a connected to the corresponding bonding pads 6a and the inner lead portions 5a of the dummy leads 5 connected to the corresponding dummy pads 6b.

With the reduction in the size of semiconductor integrated circuit devices, there have been increases in the resistance at the contact portions of metal interconnections and in the incidence of contact failure. To solve these problems, the present invention provides a novel interconnection structure. Namely, a metal interconnection which has a barrier metal layer formed thereunder and which is also used to form electrode lead-out portions for external connection is arranged such that, among the following portions, that is, electrode portions of a plurality of elements fabricated on a semiconductor substrate in the form of an integrated circuit, interconnection portions between these elements, and the above-described electrode lead-out portions for external connection, those portions of the interconnection layer which are defined as the electrode portions of the elements and the interconnection portions are isolated from the semiconductor substrate by means of a barrier metal layer, while those portions of the interconnection layer which are defined as the electrode lead-out portions for external connection are formed not through the barrier metal layer but directly on the interlayer insulating layer.

Semiconductor integrated circuit device and process for producing the

Growing community of inventors

Hino, Japan

Seiichi Ichihara