Nec Corporation

Seiichi Hannai

Yoshinori Matsui

Takeo Fujii

Hiroshi Furuta

Masaki Kawaguchi

A semiconductor integrated circuit device is configured using a DRAM and an SRAM between which data transfer is performed by way of a data transfer circuit using data transfer bus lines. Herein, the DRAM is divided into at least two DRAM arrays, each of which contains a number of columns each consisting of memory cells. In addition, the columns are arranged in mixture in connection with external I/O terminals respectively in such a way that columns respectively containing memory cells which are simultaneously subjected to read operations within a same cycle are arranged not to adjoin each other. Thus, it is possible to reduce a probability in which multiple memory cells which are simultaneously subjected to read operations within the same cycle exist within a range of an area under influence of charged particles, which are produced locally due to neutrons. Even if data of memory cells which are concentrated at a certain region are simultaneously placed under influence of the charged particles, it is possible to remarkably reduce a number of chances in that multiple bits of data being read out to the external I/O terminals go defective simultaneously.

Semiconductor integrated circuit device

A semiconductor memory device has a plurality of memory cell sub-arrays selectively used as a data storage for prohibiting a defective memory cell sub-array from a data access, and a shifting circuit couples the available memory cell sub-arrays to input and output data buffer circuits higher in a priority than another input and output data buffer circuit regardless of the location of the defective memory cell sub-array in the plurality of memory cell sub-arrays so as to share a printed circuit board between the semiconductor memory devices with the partially available memory cell sub-arrays.

Semiconductor memory device having shifting circuit connected between

A semiconductor memory device having an improved arrangement of bit lines which can operates stably, is disclosed. The memory device comprises a plurality of first bit line pairs, a plurality of second bit line pairs, and a plurality of sense amplifiers, a control circuit for connecting either of the first bit line pairs and the second bit line pairs to the sense amplifiers, and is featured in that the first and second bit line pairs are alternately arranged in parallel one by one.

Semiconductor memory device having improved sense amplifier arrangement

A dynamic type semiconductor memory device with an improved bit line arrangement is disclosed. The memory device comprises at least first and second pairs of bit lines and a sense amplifier having a pair of input terminals to which one pair of bit lines among the first and second bit line pairs are selectively connected, and is featured in that the bit lines of the first bit line pair and the bit lines of the second bit line pair are alternately arranged in parallel.

Semiconductor memory device with improved bit line arrangement

For elimination of mis-decoding operation, there is disclosed a decoder unit comprising a logic gate having input nodes respectively supplied with data bits of an input signal and carried out a logical operation to decide a logic level at an output node thereof, a precharging transistor responsive to a precharging signal and providing a conduction path between a source of positive voltage and the output node of the logic gate for charging the output node of the logic gate to a positive precharging level, an output circuit responsive to the logic level at the output node of the logic gate for producing an output signal, and a compensating transistor responsive to the voltage level at the output node of the logic gate and operative to provide a conduction path between the output node of the logic gate and the source of positive voltage, so that the compensating transistor allows an excess voltage to be discharged from the output node to the source of positive voltage, thereby preventing the decorder unit from the mis-decoding operation due to the excess voltage level at the output node of the logic gate.

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Tokyo, Japan

Seiichi Hannai