Sanyo Electric Co., Ltd.

Atr Optical & Radio Communications Research Laboratories

Seiichi Banba

Atsushi Wada

Tetsuro Sawai

Tsutomu Yamaguchi

Hisanori Uda

Minoru Sawada

Yasoo Harada

Norihiro Nikai

Yasuhiro Kaizaki

Kohji Sakata

The potential of a source terminal of a transistor is fixed; a load is connected to a drain terminal of the transistor; and an input signal is received by a gate terminal of the transistor. A series circuit including an inductor and a capacitor connected in series is provided between a connection point of the drain terminal of the transistor and the load and an output terminal of a high-frequency circuit. A band-pass filter having a prescribed characteristic is configured by an output equivalent circuit expressing an output impedance of the transistor, the load, and the series circuit.

High-frequency circuit

A cascade-connected transistor includes a common-source transistor which receives an input signal, and a common-gate transistor which is connected to a drain terminal of the common-source transistor and outputs an output signal. A band-pass filter receives the output signal of the cascade-connected transistors. An adjustment circuit is interposed between the drain terminal and the gate terminal of the common-gate transistor, and adjusts the output impedance of the cascade-connected transistor.

Amplifier for use in radio-frequency band

An analog-to-digital conversion apparatus which has a variable resolution and allows a reduction in power consumption. This apparatus comprises an analog-to-digital converter (ADC) of parallel type, a controller, and an interpolation circuit. The analog-to-digital converter has a plurality of comparators connected in parallel, each for comparing potentials of an analog input signal and a reference signal. The controller generates a control signal for controlling the resolution of the analog-to-digital converter. Specifically, the controller controls the number of comparators (CMP) to operate by means of the control signal, thereby determining the resolution. The interpolation circuit interpolates the output data of the comparators that are disabled depending on the resolution. The controller avoids simultaneous operation of two adjoining comparators when the analog-to-digital converter is operated at a resolution lower than its maximum resolution.

Analog-to digital converter and analog-to digital conversion apparatus

The collectors of transistors are connected via respective resistances to a power supply terminal receiving a power supply voltage. The emitters of the transistors are connected to a ground terminal via respective resistances. A shunt resistance, a FET, and a shunt resistance are connected in series between nodes connected to the respective emitters of the transistors. The gate of the FET is connected via a resistance to a control terminal receiving a control voltage. The shunt resistances and FET form a variable resistance circuit.

Variable impedance circuit, variable gain differential amplifier, multiplier, high-frequency circuit and differential distributed amplifier

An FET is connected between the emitters of first and second transistors. The emitter of the first transistor is connected to a ground terminal through a plurality of resistors and the emitter of the second transistor is connected to the ground terminal through a plurality of resistors. Another FET is connected between a node between the plurality of resistors on one side and a node between the plurality of resistors on the other side. The gates of the FETs are connected to a control terminal receiving a control voltage through resistors respectively. The resistors and the FETs form a variable resistance circuit. Alternatively, two FETs are serially connected between nodes connected to the emitters of the first and second transistors. Another FET is connected between a node between the two FETs and a ground terminal. The gates of the two FETs are connected to a control terminal receiving a control voltage through resistors respectively. The gate of the other FET is connected to a control terminal receiving a control voltage through a resistor. The control voltages change complementarily to each other. The FETs form a variable resistance circuit.

Variable gain differential amplifier and multiplication circuit

A first circuit which is constituted by a thin film resistor is connected between the collector of a transistor and a power supply terminal, and a second circuit which is constituted by a semiconductor resistor is connected between the emitter of the transistor and a grounding terminal. The film thickness of a thin film resistor is set to not more than its skin depth at a frequency to be compensated for.

High frequency circuit with thin film resistor

A switching circuit device including a multi-gate field effect transistor having a plurality of gate electrodes between a drain electrode and a source electrode, a low resistor having its one end connected between the gate electrodes, and a high resistor connected between the other end of the low resistor and any one of the drain electrode, the source electrode and the end of the other low resistor.

Switching circuit device and semiconductor device

A optical divider equally divides a optical carrier into first and second optical carriers. A 180.degree. divider divides an RF sub-carrier signal into first and second RF sub-carrier signals whose phases are 180.degree. inverted from each other. An electro-optic modulator modulates the first optical carrier with the first RF sub-carrier signal and outputs a first optical signal. An electro-optic modulator modulates the second optical signal with the second RF sub-carrier signal and outputs a second optical signal. Photodiodes convert the first and second optical signals transmitted by the optical fibers into first and second electric signals, respectively. A 180.degree. combiner inverts by 180.degree. the phase of the first electric signal and combines it with the second electric signal.

Optical modulation device and fiber optic communication system

In a quarter-wavelength coupled line type directional coupler including a first dielectric layer having first and second surfaces parallel to each other, a ground plane conductor is formed on the first surface of the first dielectric layer, and two coupled microstrip conductors each having a quarter wavelength are formed on the second surface of the first dielectric layer, arranging close to each other so as to be electromagnetically coupled with each other. Further, a second dielectric layer is formed on the second surface of the first dielectric layer, on which the coupled microstrip conductors are formed, and a floating potential conductor is formed on the second dielectric layer, arranging close to the microstrip conductors so as to be electromagnetically coupled with the coupled microstrip conductors. Then a cut portion is formed in the ground plane conductor so that the ground plane conductor is separated apart from the coupled microstrip conductors by a predetermined distance.

Growing community of inventors

Oogaki, Japan

Seiichi Banba