Kabushiki Kaisha Toshiba

Seiichi Aritome

Kazuhiro Shimizu

Riichiro Shirota

Takashi Mori

Tomoharu Tanaka

Ken Takeuchi

Yoshiyuki Tanaka

Kenichi Imamiya

Hideko Oodaira

Toshitake Yaegashi

Masaki Momodomi

Kazuhito Narita

Yoshihisa Iwata

Yuji Takeuchi

Yasuo Itoh

Hiroshi Watanabe

Hideko Odaira

Hideo Kato

Masamichi Asano

Yutaka Okamoto

Hiroto Nakai

Kaoru Tokushige

Tetsuo Endoh

Ryouhei Kirisawa

Hirohisa Iizuka

Akira Goda

Hiroaki Hazama

Toru Tanzawa

Koji Sakui

Susumu Shuto

Gertjan Hemink

Naoki Koido

Fujio Masuoka

Kazunori Ohuchi

Toshiharu Watanabe

Wakako Moriyama

Fumitaka Arai

Norihisa Arai

Shigeyoshi Watanabe

Shinji Satoh

Ryozo Nakayama

Toshiki Seshita

Akihiro Nitayama

Takehiro Hasegawa

Fumio Horiguchi

Tsuneaki Fuse

Tohru Maruyama

Takuya Nakamura

Osamu Ikeda

Tadashi Iguchi

Hiroaki Tsunoda

Hiroshi Nakamura

Akira Shimizu

Eiji Kamiya

Toshiyuki Hayakawa

Hitoshi Araki

Yuuichiro Murahama

Masamitsu Yahata

Kunihiro Terasaka

Masashi Umemura

Kauhito Narita

Tetsuro Endoh

In a non-volatile semiconductor memory device and a method for manufacturing the device, each memory cell and its select Tr have the same gate insulating film as a Vcc Tr. Further, the gate electrodes of a Vpp Tr and Vcc Tr are realized by the use of a first polysilicon layer. A material such as salicide or a metal, which differs from second polysilicon (which forms a control gate layer), may be provided on the first polysilicon layer. With the above features, a non-volatile semiconductor memory device can be manufactured by reduced steps and be operated at high speed in a reliable manner.

Non-volatile semiconductor memory device and its manufacturing method

A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.

Semiconductor memory device capable of realizing a chip with high operation reliability and high yield

A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.

Nonvolatile semiconductor memory

A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.

A method for manufacturing a nonvolatile semiconductor memory device including: forming a first and a second stacked gate structures, each of which including a first polysilicon layer formed on a silicon substrate via a gate insulator, an inter-gate insulator formed on the first polysilicon layer, a second polysilicon layer formed on the inter-gate insulator, and a cap layer formed on the second polysilicon layer, respectively; forming a interlayer insulator between the first and the second stacked gate structures, the interlayer insulator covering upper surfaces of the cap layer; planarizing the interlayer insulator by using the cap layers as a stopper; removing the cap layers so that the second polysilicon layers are exposed; masking the exposed second polysilicon layer of the first stacked gate structure by a photoresist film; removing the second polysilicon layer and the inter-gate insulator of the second stacked gate structure so that the first polysilicon layer of the second stacked gate structure is exposed; removing the photoresist film so that the second polysilicon of the first stacked gate structure is exposed; and forming conductive material layers, including a metal, on the exposed first polysilicon layer of the second stacked gate structure and the exposed second polysilicon layer of the first stacked gate structure.

Nonvolatile semiconductor memory and manufacturing method thereof

A nonvolatile semiconductor memory includes a trench isolation provided in a semiconductor substrate and an interlayer insulator provided on the semiconductor substrate. The trench isolation defines an active area extending in a first direction at the semiconductor substrate. The interlayer insulator has a wiring trench extending in a second direction intersecting the first direction. A first conductive material layer is provided at the cross-point of the active area and the wiring trench so that it is insulated from the active area. A second conductive material layer is provided in the wiring trench so that it is insulated from the first conductive material layer. A metal layer is provided in the wiring trench so that it is electrically in contact the second conductive material layer.

A method for manufacturing a nonvolatile semiconductor memory device having a step of forming a first gate electrode on a peripheral circuit portion and a second gate electrode on a memory cell portion, a step of introducing impurity into the peripheral circuit portion and memory cell portion, a step of forming a first insulating film above at least the memory cell portion, and a step of annealing the semiconductor substrate into which the impurity has been introduced. The first gate electrode has a first gate length. The second gate electrode has a second gate length shorter than the first gate length.

Nonvolatile semiconductor memory device and method for manufacturing the same

Growing community of inventors

Yokohama, Japan

Seiichi Aritome