Micron Technology Incorporated

Skhynix Inc.

Hynix Semiconductor Inc.

Intel Corporation

Other

Micron Corporation

Seiichi Aritome

Akira Goda

Di Li

Kirk D Prall

Behnam Moradi

Chris Larsen

Todd A Marquart

Alessandro Torsi

Carlo Musilli

Hyun-Seung Yoo

Angelo Visconti

Sung-Jin Whang

Haitao Liu

Soo Jin Wi

Mattia Robustelli

Nam-Jae Lee

Silvia Beltrami

Soon Ok Seo

Jeffrey C Antosh

Soojin Wi

Christian Monzio Compagnoni

Alessandro Sottocornola Spinelli

Roderick C Frianeza

Sang Bum Lee

Eun-Seok Choi

Sang Hyun Oh

Han-Soo Joo

Sung-Kye Park

Seok-Kiu Lee

Gyu-Seog Cho

Sung-Joo Hong

A trim set register for a memory device has a plurality of individual trim settings. Each trim setting has a program trim value, a step-up trim value, and a program pulse width. A trim setting may be assigned to a portion of the memory device based on a program speed of the portion of the memory device.

Program and read trim setting

A method and apparatus for setting trim parameters in a memory device provides multiple trim settings that are assigned to portions of the memory device according to observed or tested programming speed and reliability.

A semiconductor memory device includes a memory array including memory blocks stacked in a plurality of layers over a substrate and an operation circuit suitable for performing a read operation and a program loop to memory cells included in the memory blocks, wherein word lines of the memory blocks are coupled to each other and a pair of the memory blocks are arranged vertically adjacent to each other and share bit lines.

Three dimensional semiconductor memory device with line sharing scheme

A nonvolatile memory device includes a channel vertically extending from a substrate, a plurality of memory cells stacked along the channel; a source region connected to a first end portion of the channel, and a bit line connected to a second end portion of the channel, wherein the first end portion of the channel that adjoins the source region is formed as an undoped semiconductor layer or a semiconductor layer doped with P-type impurities.

Nonvolatile memory device and operating method thereof

A method of operating a semiconductor memory device includes performing a first program operation in order to raise threshold voltages of memory cells, performing a program verification operation for detecting fast program memory cells, each having a threshold voltage risen higher than a first sub-verification voltage from a second sub-verification voltage or lower, by using a target verification voltage and the first sub-verification voltage and the second sub-verification voltage which are sequentially lower than the target verification voltage, and performing a second program operation under a condition that an increment of each of threshold voltages of memory cells, which is lower than the target verification voltage, is greater than an increment of the threshold voltage of each of the fast program memory cells.

Semiconductor memory device and method of operating the same

A semiconductor device includes an operation circuit formed on a top surface of a semiconductor substrate, a memory array formed over the operation circuit, an inner pad group formed on an intermediate layer between the operation circuit and the memory array and coupled to the operation circuit, a first outer pad group formed on a bottom surface of the semiconductor substrate, and a wiring structure passing through the semiconductor substrate, and coupling the inner pad group to the first outer pad group.

Semiconductor device

A method for operating a non-volatile memory device includes performing an erase operation onto a memory block including a plurality of memory cells, and performing a first soft program operation onto all the memory cells of a string, after the erase operation, grouping word lines of the string into a plurality of word line groups, and performing a second soft program operation onto memory cells coupled with the word lines of each word line group.

Method for operating non-volatile memory device

A semiconductor device and a method of operating the same. The semiconductor device may include a plurality of memory blocks. Each of the plurality of memory blocks may include a plurality of cell strings extending substantially perpendicular to a semiconductor substrate, the plurality of cell strings sharing a plurality of bit lines, and a plurality of source lines respectively connected to the cell strings and word lines. Page buffers, connected to the bit lines, may store data. A selection switch portion may selectively transmit a voltage corresponding to data stored in the page buffers, and voltages supplied from an external source, to the bit lines and the source lines during the program operation, the read operation and the erase operation. A control circuit may control the page buffers and the selection switch portion.

Semiconductor device and operation method thereof

A nonvolatile memory device includes a substrate having active regions that are defined by an isolation layer and that have first sidewalls extending upward from the isolation layer, floating gates adjoining the first sidewalls of the active regions with a tunnel dielectric layer interposed between the active regions and the floating gates and extending upward from the substrate, an intergate dielectric layer disposed over the floating gates, and control gates disposed over the intergate dielectric layer.

Nonvolatile memory device and method for fabricating the same

A semiconductor device includes a first memory block including first vertical strings, a second memory block including second vertical strings coupled in series with the first vertical strings, wherein the second memory block is stacked on the first memory block, first bit lines located between the first memory block and the second memory block and electrically coupled to the first and second vertical strings, first source lines located under the first memory block and electrically coupled to the first vertical strings, and second source lines located above the second memory block and electrically coupled to the second vertical strings.

A semiconductor system includes a data storage unit including memory blocks, a circuit group and a control circuit, wherein the memory blocks store data therein and are arranged in a longitudinal direction and a vertical direction. The circuit group is suitable for performing a program, read or erase operation on the memory blocks, and the control circuit controls the circuit group. A memory control unit is suitable for controlling the data storage unit, wherein each of the memory blocks includes a plurality of sub-memory blocks. The sub-memory blocks arranged in the longitudinal direction share bit lines and do not share word lines and source lines. Further, the sub-memory arranged in the vertical direction share the bit lines or the source lines.

Semiconductor system and method of operating the same

A semiconductor device includes vertical channel layers, control gates and interlayer insulating layers stacked alternately with each other on the substrate and surrounding the vertical channel layers, floating gates interposed between the vertical channel layers and the control gates and separated from each other by the interlayer insulating layers, and charge blocking layers interposed between the floating gates and the control gates.

Method of manufacturing a semiconductor device

A semiconductor memory device includes a memory array including memory blocks stacked in a plurality of layers over a substrate, first lines coupling word lines of memory blocks arranged in even-numbered layers, and second lines coupling word lines of memory blocks arranged in odd-numbered layers.

Growing community of inventors

Boise, ID, United States of America

Seiichi Aritome