Hitachi, Ltd.

Renesas Technology Corp.

Seigou Yukutake

Yutaka Kobayashi

Koichiro Ishibashi

Shuji Ikeda

Toshiaki Yamanaka

Satoshi Meguro

Naotaka Hashimoto

Atsushi Hiraishi

Atsuyoshi Koike

Nobuyuki Moriwaki

Yasuyuki Kojima

Katsuro Sasaki

Shigeru Takahashi

Minehiro Nemoto

Soichiro Hashiba

Isamu Kuramoto

Noboru Akiyama

Kazuyuki Kamegaki

Nobuyasu Kanekawa

Hiroyuki Shoji

Hiroyuki Miyazawa

Kyoichiro Asayama

Tatsumi Yamauchi

Takashi Akioka

Jun Murata

Kinya Mitsumoto

Akihiro Tamba

Takayuki Iwasaki

Kazuhisa Takami

Katsuhiro Furukawa

Tomoyuki Someya

Yusuke Takeuchi

Toshikazu Okubo

Hideyuki Miyazawa

Masahiro Iwamura

Mutsuhiro Mori

Ryuichi Saito

Akihiko Kanouda

Hideo Maejima

Takahiro Nagano

Tasao Soga

Fumiyuki Kobayashi

Fumio Nakano

Hiroaki Hachino

Yasuo Shima

Mamoru Sawahata

Yasuhiko Kohno

Katsuhiro Higuchi

A bi-directional DC-DC converter uses a transformer for both step-down and step-up operations. A switching frequency for operating a switching device is set separately for the step-down and step-up operations. When, for example, the switching frequency during the step-up operation is lower than the switching frequency during the step-down operation, the range in which the duty ratio in PWM control can be controlled is widened, compensating for step-up ratio insufficiency. Conversely, step-down ratio insufficiency is compensated for by making the switching frequency during the step-down operation lower than the switching frequency during the step-up operation.

Bi-directional DC-DC converter and control method

The DC-DC converter connects a first and a second switching circuit for converting power mutually between direct current and alternating current respectively to a first DC power source and a second DC power source and has a transformer between the AC terminals thereof. Here, between the AC terminals of the second switching circuit and the negative pole terminal of the DC power source, a voltage clamp circuit composed of a series unit of switching devices with a reverse parallel diode and a clamp condenser is connected. An isolated bidirectional DC-DC converter which prevents a reduction in a circulating current at time of buck and an occurrence of a surge voltage at time of voltage boost and realizes highly efficiency, low noise, and miniaturization is provided.

Isolated bidirectional DC-DC converter

A primary side circuit and a secondary side circuit are provided on first and second semiconductor substrates, respectively. A first capacitive insulator on the first substrate electrically insulates and isolates between the primary and secondary side circuits while permitting signal transmission between these circuits. A second capacitive insulator on the second semiconductor substrate electrically isolates the primary and secondary side circuit while permitting signal transmission therebetween. First and second frames are provided for input and output of signals to and from the primary and secondary side circuits. External electrodes of the first and second capacitive insulators are connected together by a third lead frame via a conductive adhesive body including more than one solder ball. The first and second substrates and the lead frames are sealed by a dielectric resin.

Semiconductor device having capacitive insulation means and communication terminal using the device

An ignitor comprising a circuit with a millisecond order time constant and with a minimum circuit size and area, which is capable of self-shutdown without leading to erroneous ignition upon detection of an abnormality. An ignitorcapable of self-shutdown upon detection of an abnormality comprises an abnormality detection circuitwhose rise output is applied to the gate of a self-shutdown MOSFETvia an integration circuitcomprised of a diodeand a capacitor. The gate voltage of IGBT, which is a main-current switching device, can be decremented.

Integration circuit, decrement circuit, and semiconductor devices

Semiconductor device including primary and secondary side circuits on first and second substrates with capacitive insulation

Wire bonding or printed wiring board leads or, alternatively, lead frames or equivalents thereof are used to electrically connect external electrodes of high withstand voltage capacitors formed on a plurality of semiconductor chips. A driver circuit for signal transmission or receiver circuit for signal receipt formed on the semiconductor chips are electrically connected with substrate-side electrodes of said high withstand voltage capacitors, causing the plurality of semiconductor chips to be received within either a single package or a single module. Using this arrangement, a semiconductor device is capable of achieving both dielectricity and size reduction.

Semiconductor device and communication terminal using thereof

The hardware of an over-sampling A/D and D/A converter is provided, which hardware is capable of being operated with either kind of software: one corresponding to a first method in which the over-sampling ratio is fixed and the other corresponding to a second method in which the over-sampling ratio is variable. The value N written on the pseudo-frequency-dividing-ratio-register and the value N written on the pseudo-over-sampling-ratio-register are converted through a user interface into the frequency dividing ratio N by the conversion circuit and the converted result is written in the frequency-dividing-ratio-register

Over-sampling A/D, D/A converter

A small sized semiconductor device having a high insulating performance between a primary side circuit and a secondary side circuit is realized. A circuit region plural first and second terminal electrodes connected to the circuit region and an insulation-separation region for separating electrically the first terminal electrodes from the second terminal electrodes, and for transmitting signals between the first and the second terminal electrodes are formed onto a semiconductor chip and the insulation-separation region is provided between the first and second terminal electrodes. The interval between the first and the second terminal electrodes on the same semiconductor chip can be separated with high insulating performance.

Semiconductor device

In order to reduce the consumption of power of an isolator interface and an ADC, it is proposed to operate a calling signal reception or Caller ID signal reception function only with power supplied from the system switch while maintaining the on-hook condition of a telephone. At the time of normal operation, the output of the analogue digital converter is input to an isolator through the isolator interface, and at the time of the calling signal reception or the caller identification information reception, the output of the analogue digital converter is input directly to the isolator.

Line interface circuit and information communication apparatus using it

A semiconductor device and a computer system, incorporating the same, is capable of capturing an external signal at a high speed and stably operating independent of the duty ratio of a clock signal. An external signal ADD is captured into an address latch 22 by a level latch. The level latch is controlled to a through state at the timing in which the external signal is decided and controlled to a latched state in the decision period of the external signal. A pulse generation circuit controls the timing for switching a latch to the through state to a desired timing by a pulse generation circuit 30 in a chip. According to the above structure, the capture of the external signal ADD can be accelerated because the capture of the signal is determined by the setup timing. Moreover, because a latching period is controlled by the pulse generation circuit in the chip, operations are performed in a stable manner without having to depend upon the pulse width of an external clock CLK.

Semiconductor device capable of holding signals independent of the pulse

Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially. The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines. The source line is formed of a conductive layer identical to that of the word line. The individual data lines of the complementary data line are formed of an identical conductive layer which is different from that of the word line and the source line. The identical conductive layer between the word line and source line and the complementary data line is formed with two word lines: a main word line extended in the first direction identical to that of the word line and source line and used by adopting the divided word line system: and a sub-word line used by adopting the double word line system.

SRAM having load transistor formed above driver transistor

Semiconductor integrated circuit device and process for fabricating the

Herein disclosed is a semiconductor integrated circuit device comprising an SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs, and a method of forming this device. The gate electrodes of the drive MISFETs and of the transfer MISFETs of the memory cell, and the word lines, are individually formed of different conductive layers. The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The source line is formed of a conductive layer identical to that of the word line. An oxidation resisting film is formed on the gate electrodes of the drive MISFETs so as to reduce stress caused by oxidization of edge portions of these gate electrodes, and to reduce a resulting leakage current. A thickness of an oxide film formed on gate electrodes of the transfer MISFETs and word lines is thicker than an oxide film formed on gate electrodes of the drive MISFETs, so that data line pads can be formed in self-alignment with the oxide film and side wall spacers on the gate electrodes of the transfer MISFETs.

Process for fabricating a semiconductor integrated circuit device

Growing community of inventors

Hitachinaka, Japan

Seigou Yukutake