Hitachi, Ltd.

Other

Seigoh Yukutake

Takashi Akioka

Masahiro Iwamura

Noboru Akiyama

Yutaka Kobayashi

Nobuyasu Kanekawa

Atsuo Watanabe

Yasuyuki Kojima

Shinichiro Mitani

Kinya Mitsumoto

Minehiro Nemoto

Takayuki Iwasaki

Katsuhiro Furukawa

Chiyoshi Kamada

Masatsugu Amishiro

Takayuki Oouchi

Kazumasa Yanagisawa

Ryoichi Hori

Akihiko Emori

Goro Kitsukawa

Junichi Sakano

Naoki Sakurai

Hiroyuki Miyazawa

Shinji Nakazato

Sadayuki Ohkuma

Shuichi Miyaoka

Kyoichiro Asayama

Akihiro Tanba

In a level shift circuit, when a power-source voltage variation dV/dt of a high voltage side occurs and influences on a logic level of a circuit, the passing through of a malfunction signal is masked and prevented in the first and second logic circuits, by a signal from a time-constant generation circuit or a portion where a power voltage variation occurs in advance, by utilizing the fact that this variation occurs both at a set side and a reset side. When the power source voltage variation dV/dt is generated at a high voltage side, sufficient allowance in the timing of this masking prevents an erroneous signal from being transmitted to a flip-flop, and a control signal is transmitted from a low voltage side circuit not giving malfunction to a high voltage side circuit, even when there is a production variation in each element in semiconductor processes.

Level shift circuit and power conversion unit

A communication system is provided including a transceiver and an application controller to transmit and receive signals through the transceiver. An isolator which insulates and separates the transceiver and application controller includes primary and secondary side circuits insulated from each other on a substrate and a capacitive insulating means to transfer signals between the primary and second sides while insulating and separating the primary side circuit from the secondary side circuit.

Isolator and a modem device using the isolator

An isolator is made monolithic by forming a capacitive insulating barrier using an interlayer insulation film on the semiconductor substrate to miniaturize the modem device by the monolithic isolator.

There is provided a method of controlling an internal address signal of an RAM in which a late-write method is realized on a chip. Two sets of address registers for reading and writing are provided for each address and further a middle register is provided between the two sets of address registers. The middle register is controlled by a signal formed by obtaining the AND result of a clock signal and a write enable signal and the two sets of address registers for reading and writing are controlled only by the clock signal. A selection circuit selects outputs of the two sets of address registers as an input in accordance with the write enable signal to control an internal address.

Synchronous memory with pipelined write operation

A constant current source is connected in series to a current source circuit including a MOS transistor which is used as a current source for a differential output amplifier circuit, an emitter follower circuit or a source follower circuit used with a semiconductor integrated circuit. In a multiplex circuit, an input signal is inputted to each of base terminals of a plurality of bipolar transistors. When one input signal is selected, the bipolar transistor corresponding to the selected input signal is made to be operable with an input signal from a signal input terminal by a control circuit. The bipolar transistors corresponding to the non-selection input signals are turned OFF irrespective of potential levels of the individual input signals by current drawing circuits. There is also disclosed a semiconductor memory circuit having a plurality of memory cells, a memory cell selection scheme and a sense amplifier for amplifying data outputted from the selected memory cell, in which a constant current circuit is provided in series connection to the sense amplifier to enhance the performance characteristics of the memory circuit. Also, a plural memory array scheme is disclosed which employs multiplexing techniques connected to presense amplifier circuits of the respective memory arrays.

Memory circuit improved in electrical characteristics

A synchronous memory device is provided in which the cycle time is shorter than conventional memory devices. For example, by providing an output latch in a sense amplifier on a bit line, the time period from input of a clock signal to latching data in the output latch is shortened. In case of plural bit lines, a selector for selecting data in a plural output latch and a latch for latching a sense amplifier selection are provided.

Memory device for synchronously reading and writing data

A memory device comprising a memory array having a plurality of bits, including parity bits, and comprising a plurality of memory blocks, and a bit structure changing section for changing the input/output bits of the memory array, wherein the number of the memory blocks are prescribed to be an integral multiple of three and the input/output bits of the plurality of memory blocks are even. Thereby, the bit structure of the semiconductor memory, having parity bits and which is capable of changing the input/output bits to a plurality of bit structures, can be changed while maintaining the bit structure of the memory blocks even and without increase in propagation delay time.

Semiconductor device

A multiplex circuit is disclosed in which a plurality of bipolar transistors are combined and in which the respective base terminals thereof are used as inputs, thereby to construct an emitter follower type multiplex circuit. In such an emitter follower type multiplex circuit, the multiplexing function of non-selection/selection is effected by controlling the base potential of the respective bipolar transistors by providing a MOS transistor between each base and a high potential of the power source through a resistor and a current drawing circuit. In accordance with such a scheme, when a selection of one input signal is made, the bipolar transistor corresponding thereto is permitted to turn ON on the basis of an input signal supplied to the base terminal thereof. The bipolar transistors corresponding to the non-selection input signals are maintained OFF, through activating the current drawing circuits associated therewith, irrespective of the potential levels of the incoming input signals supplied to the base terminals thereof. In the emitter follower type multiplex circuit, a constant current source is also provided between the commonly connected emitters of the bipolar transistors and the power source of low potential. The multiplex arrangement effected can be of the collector dot type multiplex circuit. Such multiplex circuits are used with a semiconductor integrated circuit such as a memory circuit.

Multiplex circuit arrangement for use with a semiconductor integrated

An area of a semiconductor chip, on which a memory is disposed, is divided into a plurality of memory blocks and redundant memory blocks, each memory block is divided into a plurality of unit arrays of columns for replacing, each redundant memory block is divided into a plurality of unit arrays of redundant columns, a plurality of memory cells are disposed in each unit array of columns for replacing and each unit array of redundant columns, a memory cell group in each unit array of columns for replacing is connected to a word line and a data line, a redundant memory cell group of each unit array of redundant columns is connected to a redundant word line and a redundant data line, a first data selection circuit for controlling data selection with respect to the unit array of redundant columns is disposed in each memory block, a second data selection circuit for controlling data selecting with respect to the unit array group of redundant columns is disposed in each redundant memory block, and a third data selection circuit for selecting and transmitting only data selected either of the data selection circuit is disposed, wherein, if each memory block has no defect, data selected by the first data selection circuit, that is, data selected from the unit array of columns for replacing of each memory block is transmitted as it is by way of the third data selection circuit, if any one of the memory blocks has a defect, data selection with respect to the unit array of columns for replacing that has encountered the defect is inhibited, the unit array of redundant columns of the redundant memory block is instructed in place of the unit array of columns for replacing that has encountered the defect, and data is, by the second data selection circuit, selected from the selected unit array of redundant columns in place of the replacement unit array that has encountered the defect as to transmit the selected data by way of the third data selection circuit.

Semiconductor memory with multiple sets & redundant cells

A small and reliable semiconductor device is provided in a substrate which has an isolation trench and a capacitor trench. The isolation trench isolates a bipolar transistor from other semiconductor devices, and the capacitor trench provides capacitance to a memory cell which is formed in the substrate. The interior of the device isolation trench is kept in a floating state with respect to the surrounding semiconductor regions by forming an insulating film over the inner surface of the trench. In the capacitor trench, insulating layers and resilient conductive layers are formed alternately to form capacitance between the opposing conductive layers.

Growing community of inventors

Hitachi, Japan

Seigoh Yukutake