Tokyo Shibaura Electric Co., Ltd.

Kabushiki Kaisha Toshiba

Tokyo Shibaura Denki Kabushiki Kaisha

Seigo Suzuki

Seiji Eguchi

Yoshiaki Moriya

Hiroshi Iwahashi

Shinichi Yoshioka

Kunio Muramatsu

Masumi Kawakami

Sigeru Nose

Keiji Uemori

Yukihiko Yabe

Disclosed are semiconductor devices employing chips comprising highly integrating semiconductor elements, and having various means for controlling temperature increase of the chips. These means comprise three approaches: means for controlling heat generation by adjusting clock frequencies to be supplied to the chips respectively; means for suppressing heat generation by suitably arranging the wiring construction of the chip substrate; and means for suppressing heat generation of sub-chips by a prarallel process such as optical communication between the sub-chips.

Semiconductor device enabling temperature control in the chip thereof

An operation unit includes at least one processing circuit, a completion detection circuit, and a synchronous clock generator. The detection circuit is connected to the processing circuits, and detect the completion of the operations carried out by the processing circuit. The synchronous clock generator generates a clock signal of the operation unit according to the speed of the processing circuit. If the unit includes plural processing circuits, detection circuits are connected to the processing circuits respectively. And a synthesis unit is connected to the detection circuits for receiving completion signals and prepares a general monitor flag to determine the slowest speed in the plural processing circuits. The clock signal is generated according to the slowest speed. Even if the operation speeds of LSIs scatters due to manufacturing variations, clock frequencies proper for a given LSI are dynamically and flexibly set so that every LSI may demonstrate its maximum performance.

Operation unit and method for controlling processing speed of the same

Disclosed are semiconductor devices employing chips comprising highly integrating semiconductor elements, and having various means for controlling temperature increase of the chips. These means comprise three approaches: means for controlling heat generation by adjusting clock frequencies to be supplied to the chips respectively; means for suppressing heat generation by suitably arranging the wiring construction of the chip substrate; and means for suppressing heat generation of sub-chips by a parallel process such as optical communication between the sub-chips.

A plurality of stages of MOS gate circuits are connected in series and are driven with a 2-phase AC power source. The alternating speed of the power source is slower than the operation speed of internal circuit elements of the MOS gate circuits. A cutoff device such as a transistor is arranged on each side of each of the MOS gate circuits and is connected to the power source. The cutoff devices of each MOS gate circuit are conductive only when one phase of the power source is at high potential and the other at low potential. When the MOS gate circuit of a given stage (N.sub.i) is inactive, the MOS gate circuit of the next stage (N.sub.i+1) holds charge, to reduce an energy loss.

Adiabatic MOS logic and power supplying method and apparatus

A line memory for speed conversion, whose data rates of write into and read from a memory cell (1) differ from each other, has a write circuit (2, 3, 4) for writing input data (D.sub.in) into the cell (1) at a predetermined rate and resetting the write address of the cell (1) at a predetermined period, a read circuit (5, 6, 7) for reading data (D.sub.out) from cell (1) at a rate different from the write rate and resetting the read address of the cell (1) at the predetermined period, the first shift circuit (8) for shifting reset timing of the write address, and the second shift circuit (9) for shifting reset timing of the read address, the first and second shift circuits enabling respective setting quantities at the same value. This memory can shift both the write address reset timing and the read address reset timing while keeping both in the same condition.

Line memory for speed conversion

An image memory comprising a plurality of memory cell columns for memorizing image data, common word lines for connecting memory cells of these memory cell columns, a scanner for sequentially designating memory cells of the column on the basis of a clock signal, a column address counter for counting the clock signal to output a column address signal, a write column selector responsive to the column address signal to select a memory cell column into which image data is written, a write buffer for writing image data into the designated memory cell of the memory cell column selected by the write column selector, a read column selector for selecting a memory cell column different from the memory cell column selected by the write column selector, and a read buffer for reading image data from the designated memory cells of the memory cell column selected by the read column selector. The image memory is capable of performing write and read operations at the same time. For performing refresh operation simultaneously with read/write operation, a read/write/refresh selector may be provided instead of a read/write selector provided in the column address counter. Further, for realizing write and read operation at the same time even when a write clock signal is different from a read clock signal, the memory cell columns may be divided into a plurality of memory cell column groups, e.g., odd and even memory cell groups.

Image memory having standard dynamic RAM chips

A data delay/memory circuit includes clock-controlled data latch circuits formed with cascade-connected clocked inverters. The data delay/memory circuit also includes a clock generator for supplying the clocked inverters with clock signals. These clock signals have individual clocking phases and are sequentially generated such that the clocking phase for a final stage of the data latch circuits is ahead of that for an initial stage thereof.

Data delay/memory circuit

An analog signal is input to an A/D converting section. This A/D converting section has a D/A converter therein. The A/D converting section converts the input analog signal to a digital signal. A digital signal processing circuit receives an output signal from the A/D converting section and performs a predetermined process to this signal. A D/A converting section receives and converts an output signal of the digital signal processing circuit to an analog signal. This D/A converting section has a D/A converter with the same circuit arrangement as the D/A converter in the A/D converting section circuit and is constituted by the same circuit pattern. Therefore, the converting functions of the A/D converting section and of the D/A converting section are inverse functions of each other, so that error or distortion, which is caused in the A/D converting section, is automatically corrected when the digital signal is reconverted to the analog signal in the D/A converting section.

Analog signal processing apparatus

The majority circuit has an (n+1)/2-notation counter circuit comprising a plurality of cascade-connected binary counters. An odd number of n-bit serial data are counted by the counter circuit, and an output of the binary counter of the last stage is taken out as a majority output of the majority circuit.

Majority circuit comprising binary counter

A signal synthesizer apparatus having a parameter dependent multiplier which includes charge-coupled devices. The multiplier has a gating input to store a charge corresponding to an input signal applied thereto; a transmission circuit for selectively transferring portions of the stored input charge, the selectivity of the transmission circuit being dependent on the prescribed parameter; and an output for receiving and combining all of the charges transferred from the transmission circuit. The transmission circuit comprises a first circuit for selectively dividing the charge corresponding to the input signal into given fragments and for transferring the divided charge, and a second circuit for determining the selectivity of the dividing of the charge according to the prescribed parameter. The rate of the dividing of charge corresponds to the multiplicative coefficient of the multiplier.

Signal synthesizer apparatus

A memory access control system selects a program mode to carry out a cycle steal operation in response to a logic '1' condition of a predetermined bit position included in a command and selects a direct memory access mode to effect a direct memory access in response to a logic '0' condition of the predetermined bit position.

Memory access control system

An information transferring apparatus comprises a central processing unit, and an input/output unit, a first-in first-out stack having a plurality of memory elements connected in series and being disposed between the central processing unit and the input/output unit, a command register which is set to a predetermined state under program control by the central processing unit, and a control circuit which receives a signal produced from the command register when the command register is set to a predetermined state and applies a signal designating the memory element which is to be the first memory element of the first-in first-out stack from which information is to be transferred and permits the information stored in the first memory element to be read out directly to the input/output unit.

Information transferring apparatus

A signal synthesizer apparatus having a parameter dependent multiplier which includes charge-coupled devices. The multiplier has a gating input to store a charge corresponding to an input signal applied thereto; a first set of transmission gates for selectively transferring portions of the stored input charge, the selectivity of the transmission gates being dependent on a prescribed parameter; a plurality of intermediate electrodes for storing the charges transferred by the transmission gates; a second set of transmission gates for transferring the charges stored by the intermediate electrodes; and an output electrode for combining all of the charges transferred from the intermediate electrodes by the second set of transmission gates. The signal output by the multiplier corresponds to the magnitude of the combined charges of the output electrode.

A multi-processor system includes a plurality of processors, a common shared memory, and programmable memory access priority control circuit. The programmable memory access priority control circuits includes a programmable register circuit and a priority control circuit. The programmable register circuit stores priority information designating a memory access grade priority for each of the processors, wherein the priority information is changeable either manually, by external circuit or by at least one of the processors and remains fixed irrespective of access of the memory by any of the processors until being changed. The register circuit outputs priority information signals which indicate the memory access grade priority of each of the processors. The priority control circuit receives the priority information signals from the register means, receives a memory request signal from the processors requesting memory access (i.e. use) of the common shared memory, and outputs an acknowledge signal enabling the processor having the highest memory access grade priority to use the common shared memory in accordance with the priority information.

Multi-processor system with programmable memory-access priority control

A multi-processor system having a priority control wherein jobs are transferred between processors in a multi-processor system when a new job is accepted by the system. The processors are arranged in a predetermined priority sequence and in response to an interrupt command, the system always directs a transferred job to which priority processor whose currently executing job is transferred to a lower priority processor. Jobs are transferred by shifting linkage information from one processor to the other through a common control memory in accordance with a job transfer program at each processor. When the interrupt cycle is completed, transferred jobs are returned to the processor at which they were being processed prior to the interrupt.

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Yokohama, Japan

Seigo Suzuki