Nippon Telegraph and Telephone Public Corporation

Hitachi, Ltd.

Seiei Ohkoshi

Hideo Suzuki

Nobuo Tsukamoto

Isao Ishikawa

Ichiro Ohhinata

Teiji Okamoto

Kazuyuki Yamamoto

A code converting circuit of simple construction composed of an exclusive OR circuit and a flip-flop circuit is provided on each of transmitting and receiving sides of a digital data transmission system according to a differential phase shift keying system, to convert two consecutive errors on adjacent bits peculiar to the differential phase shift keying system into only an error on a single bit. As a result, it is not required to employ a code having an excellent error-correcting capacity in the digital data transmission system, and thus a high transmission efficiency is attained by the use of a code which is relatively deficient in error correcting capacity.

Method and apparatus for eliminating double bit errosion in a

In a key telephone system including an electronic speech channel switching network and an electronic key telephone set selectively connected to central office lines by the speech channel switching network, the speech channel switching network is constituted by a pair of incoming lines connected to a pair of central office lines and a plurality of pairs of outgoing lines connected to the key telephone set. The incoming and outgoing lines are arranged in a matrix, and a plurality of controllable unidirectional switching elements are disposed respectively at four cross-points between the incoming and outgoing lines. Each switching element is connected oppositely with respect to one incoming line and to one outgoing line which comprise a pair.

Speech channel switching networks suitable for use in combination with

A memory circuit comprising a memory cell for storing information, constituted of semiconductor circuit elements and the associated circuit elements, and a control input section provided on the input side of the memory cell for controlling the memory cell, constituted of transistor means and current control means, wherein one of ON and OFF states is selected and also held in accordance with more than two logic input signals supplied to the control input section and no power is consumed to hold the OFF state.

Memory circuit

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Yokohama, Japan

Seiei Ohkoshi