Tram, Inc.

T-ram Semiconductor, Inc.

Sei-Seung Yoon

Seong-Ook Jung

Jin-Man Han

A sensing circuit including a sense amplifier to resolve a data signal generated by a memory cell is disclosed herein. The sensing circuit includes a bit line to receive the data signal, a first pre-charge device coupled to the bit line and configured to pre-charge the bit line, a device for providing a bias coupled to the bit line and configured to provide a bias to the bit line, and a reference node configured to be at least one pre-determined level. In one embodiment the pre-determined level is equal to a low potential such as ground and in another embodiment equal to a high potential such as V. One or more switching devices allows for the activation or deactivation of the pre-charge device allowing to pre-charge the bit line to a certain potential and the sensing circuit quickly and accurately determines whether a logical state of '1' or '0' is being applied to the bit line.

Single data line sensing scheme for TCCT-based memory cells

A circuit and a method are provided for facilitating control of bit lines in preparation for, or during, sense amplification of data signals from thinly capacitively-coupled thyristor ('TCCT')-based memory cells. In accordance with a specific embodiment, a circuit and method are designed, among other things, to effectively minimize power consumption by memory cells and to increase speed and reliability of sense amplification. In another specific embodiment, the circuit and method are directed to TCCT-based memory cells.

Bit line control and sense amplification for TCCT-based memory cells

The present invention provides a circuit and a method for providing nondestructive write operations and optimized memory access operations with reduced power consumption during memory access, such as during write operations. In one embodiment, a memory device comprises a memory cell configured to store a first data bit. The memory device also comprises a write access circuit coupled to the memory cell for providing a write data bit having a write data bit magnitude. The write access circuit is configured to adjust the write data bit magnitude to an intermediate logic state magnitude in a memory operation.

Circuit and method for implementing a write operation with TCCT-based memory cells

A circuit and a method are provided for facilitating control of bit lines in preparation for, or during, sense amplification of data signals from thinly capacitively-coupled thyristor (&ldquo;TCCT&rdquo;)-based memory cells. In accordance with a specific embodiment, a circuit and method are designed, among other things, to effectively minimize power consumption by memory cells and to increase speed and reliability of sense amplification. In another specific embodiment, the circuit and method are directed to TCCT-based memory cells.

Growing community of inventors

Cupertino, CA, United States of America

Sei-Seung Yoon