Samsung Electronics Co., Ltd.

Sei-seung Yoon

Yong-Cheol Bae

Byung-chul Kim

Dong-Il Seo

Sang-Pyo Hong

Chan-jong Park

Tae-seong Jang

Dong-il Seo

Il-Man Bae

Se-jin Jeong

Jei-Hwan You

Moon-Gone Kim

Gi-Hong Kim

Gi-hong Kim

Seong-Min Wi

An internal clock delay circuit of a semiconductor device and a method for delaying an internal clock of the semiconductor device. The semiconductor device includes a CAS latency signal generator that generates CAS latency signals comprising a first CAS latency signal, a second CAS latency signal and a third CAS latency signal, and an internal clock delay circuit that receives one of the CAS latency signals and an internal clock signal and delays the internal clock signal by a predetermined time in response to the received CAS latency signal. The internal clock delay circuit includes delay circuits that delay the internal clock signal, and the internal clock signal passes through only one among the delay circuits when the semiconductor device operates in the second CAS latency mode. The method includes: inputting an internal clock signal to an internal clock delay circuit, which includes delayers, of a semiconductor device; and inputting CAS latency signals to the internal clock delay circuit to determine CAS latency modes of the semiconductor device; and outputting the internal clock signal through the delay circuits as an output signal of the internal clock signal delay circuit. The internal clock signal passes through one of the delay circuits in a second CAS latency mode and passes through at least two delay circuits among the delay circuits in either a first CAS latency mode or a third CAS latency mode.

Internal clock signal delay circuit and method for delaying internal clock signal in semiconductor device

Integrated circuits and methods use a margin test voltage generator that is powered at a first power supply voltage to generate a second power supply voltage that has a magnitude that is less than the magnitude of the first power supply voltage. During a low supply voltage margin test, a first logic circuit is powered at the first power supply voltage while a second logic circuit, which is the subject of the test, is powered at the second power supply voltage. As a result, the first power supply voltage may remain at a sufficient magnitude to reliably power other devices or components that are not undergoing the low supply voltage margin test.

Integrated circuits including voltage-controllable power supply systems that can be used for low supply voltage margin testing and related methods

Integrated circuit memory devices include a control circuit that generates an active first control pulse (e.g., PR) having a first duration, in response to an active strobe pulse (e.g., /RAS) that may be generated during a data reading operation. To improve the reliability of the data reading operation and any subsequent data restore operation, particularly when the duration of the active strobe pulse is relatively short, a pulse width extension circuit is provided. The pulse width extension circuit converts the active first control pulse into an active second control pulse (e.g., PAIVCE,) having a second duration greater than the first duration. This active second control pulse is then provided as a control input to an internal voltage generator. The internal voltage generator is provided to drive a first supply signal line (e.g., AIVC,) at a first supply voltage in response to the active second control pulse. The first supply signal line may be provided as an internal supply line to one or more active circuits within the memory device. The first supply signal line may power a differential sense amplifier during data reading and data restore operations (i.e., when data is being sensed and amplified on a pair of differential bit lines). These reading and restore operations may be performed with higher reliability if the additional pulse duration provided by the pulse width extension circuit is sufficient to enable a complete recharging of the differential bit lines of the sense amplifier while a data restore operation is being performed.

Integrated circuit memory devices having improved sense and restore operation reliability

A method for fabricating a DRAM cell capacitor is applicable to a high density dynamic random access memory (DRAM) device on a semiconductor substrate wherein a storage node is formed on a buried contact pad in self-alignment. The method comprises forming a second insulator layer on the first insulator layer including the buried contact pad. An etching stopper layer is next formed on the second insulator layer. Sequentially, a third insulator layer and a first polysilicon layer are formed on the etching stopper layer. A masking layer is formed on the first polysilicon layer to define a storage node. The first polysilicon layer and the third insulator layer are sequentially etched using the masking layer until the etching stopper layer is exposed, so as to form a top via hole. A sidewall spacer is formed on both sidewalls of the top via hole. After removal of the masking layer, the etching stopper layer and the second insulator layer are sequentially etched using a combination of the first polysilicon layer and the sidewall spacer as a mask until the contact pad is exposed, so as to form a bottom via hole beneath the top via hole. A second polysilicon layer is deposited filling up the bottom and top via holes. The semiconductor substrate is planarized by CMP procedure until the third insulator layer is exposed. Finally, the third insulator layer is etched to form the cylindrical storage node having the sidewall spacer and the second polysilicon layer in self-alignment.

Method for fabricating a capacitor for a dynamic random access memory cell

Integrated buffer circuits include an output driver powered at a first power supply voltage (EVC) and a voltage boosting circuit which drives an input (DOK) of the output driver and is powered at a second power supply voltage (VINTQ) having a magnitude less than a magnitude of the first power supply voltage. An internal power supply voltage generator is provided which generates the second power supply voltage at a level which varies inversely with increases in the first power supply voltage in order to minimize timing skew associated with the output driver. This is achieved by lowering the voltage of the signal applied to the input (DOK) of the output driver to compensate for the output driver being powered at an increased first power supply voltage.

Integrated circuit devices having improved internal voltage generators

Integrated power supply voltage generators include a boosted voltage generator which generates a boosted voltage signal (Vpp) at a first level on a boosted voltage signal line during a set-up time interval, in response to an internal power supply voltage signal (VINTA*), and a circuit which is responsive to a first reference voltage (VREFA) and the boosted voltage signal (Vpp) and generates the internal power supply voltage signal (VINTA*) at a second level which is less than the first level throughout the set-up time interval.

Integrated power supply voltage generators having reduced susceptibility

A semiconductor memory device having a plurality of memory array banks, a plurality of active array voltage generators, a standby array voltage generator and a plurality of switching means is provided. The semiconductor memory device includes a plurality of memory array banks in which information is stored, a plurality of active array voltage generators connected to the memory array banks, for generating predetermined active voltages in response to memory array bank enable signals for activating the memory array banks, a standby array voltage generator for generating a predetermined standby voltage so that the memory array banks are maintained in a standby state for operation, and a plurality of switching means connected between the memory array banks and the standby array voltage generator, for disconnecting the output of the standby array voltage generator from memory array banks in response to memory array bank enable signals for activating the memory array banks. The power consumption of the semiconductor memory device is reduced.

Multi-bank memory devices having common standby voltage generator for

A column select line control circuit for a synchronous semiconductor memory device increases the time margin for writing input data to memory cells in prefetch mode by delaying the disablement of the column select lines during a write operation, thereby extending the time for writing data to the cells. The control circuit includes a column select line control circuit that generates enable and disable signals in response to an internal clock signal, and a column decoder that enables and disables a column select line in response to the enable and disable signals. In pipeline mode, the column select line control circuit generates the disable signal by delaying the internal clock signal and generates the enable signal by delaying and inverting the internal clock signal. In prefetch mode, the column select line control signal adds an additional delay to both the enable and disable signals, but only during write operations.

Method and apparatus for controlling column select lines in a

In a semiconductor memory device, a plurality of output buffers, one for each output data bit, are powered by an internal voltage control circuit so as to provide high speed operation yet minimize power consumption. The internal voltage control circuit inclues multiple internal voltage generators. Responsive to the number of output buffers in use during a read operation, one or more of the voltage generators are activated to power the output buffers. Additionally, the current capacity of each of the individual voltage generators is controlled responsive to the number of output buffers in use during the read operation, so that bandwidth of the memory device is maximized but power is not wasted.

Circuit for controlling internal voltage for output buffer of

Preferred integrated circuit memory devices have the capability of connecting a sense amplifier to multiple arrays of memory one-at-a-time or simultaneously, in response to first and second control signals, respectively. These memory devices include first and second memory arrays which have first and second pairs of differential input/output lines electrically coupled thereto, respectively. A sense amplifier is also provided having first and second pairs of differential input/output lines. To provide independent or simultaneous access to the first and second memory arrays by the sense amplifier, preferred isolation and equalization circuits are provided. With these circuits, a first electrical connection can be formed between the first pairs of differential input/output lines of the first memory array and the sense amplifier and a second electrical connection can be simultaneously formed between the second pairs of differential input/outlput lines of the second memory array and the sense amplifier, when a control signal line is in a first logic state (e.g., logic 0). These preferred isolation and equalization circuits also preclude simultaneous formation of the first and second electrical connections when the control signal line is in a second logic state (e.g., logic 1).

Integrated circuit memory devices having cross-coupled isolation gate

Voltage boosting circuits include backup voltage boosting circuits which are enabled during high current loading conditions when voltage sags in the potential of a boosted signal line(s) are encountered, and which provide independent level detection capability to bypass main voltage level detectors when relatively severe voltage sags are anticipated. In particular, voltage boosting circuits are provided which contain a main voltage boosting circuit and a backup voltage boosting circuit therein. The main voltage boosting circuit is typically powered at a first reference potential (e.g., Vcc) and preferably contains a main level detector, a built-in oscillator and a main pump coupled in series to drive a signal line (e.g., Vpp) to a boosted reference potential which is greater than the first reference potential, if a potential of the signal line drops below a second reference potential. To supplement the voltage boosting capability of the main pump, a backup voltage boosting circuit is provided containing an independent voltage level detector and at least one backup pump coupled in series therewith, to drive the signal line to the boosted reference potential, if the potential of the signal line drops below a third reference potential which may be greater than or equal to the second reference potential. Accordingly, the occurrence of relatively small voltage sags in the potential of the boosted signal line (e.g., Vpp) can trigger the backup pump during anticipated high current loading conditions, while the occurrence of larger voltage sags in the potential can trigger the main pump to assist the backup pump.

Voltage boosting circuits having backup voltage boosting capability

A semiconductor memory device comprising a memory cell array including at least two banks and a desired number of voltage pumping circuits each for pumping an input voltage to a desired level. The voltage pumping circuits are driven in response to at least two bank selection control signals. The voltage pumping circuits are arranged in the semiconductor memory device in a proper manner to efficiently perform the voltage pumping operation, so as to increase the pumping efficiency. Further, the proper arrangement of the voltage pumping circuits contributes to the integration of the semiconductor memory device.

Voltage pumping circuit for semiconductor memory device

Integrated circuit chips with multiplexed input/output pads include means for expanding the functional and diagnostic capability of the circuit by increasing the effective number of input/output pads connected thereto so that more information can be provided to and from the chip. In particular, multiplexing means preferably provides the capability of accessing any one of a plurality of signal lines in the circuit from each input/output pad. This expanded capability is preferably achieved using one or more selection control signals which can be generated internally or externally to a chip containing the integrated circuit. An integrated circuit memory device, for example, preferably comprises a semiconductor substrate, a memory circuit in the substrate, a plurality of input/output pads and means, coupled to signal lines in the memory circuit, for multiplexing the plurality of input/output pads to the signal lines by electrically connecting respective ones of the signal lines to the input/output pads in response to a first select signal and electrically connecting respective others of the signal lines to the input/output pads in response to a second select signal. Because each pad on a chip can be connected to one or more signal lines, the memory circuit has a greater number of effective pads which means that a fewer number of pads on a small memory circuit chip can provide essentially the same input/output capability as a greater number of pads on a larger chip.

Integrated circuit chips with multiplexed input/output pads and methods

There is provided in the present invention a signal generator which generates a bit line equalization signal and a signal generator which generates a sense amplifier equalization signal to control the bit line equalization circuit and the sense amplifier equalization circuit, respectively. The generated bit line equalization signal and sense amplifier equalization signal both have a voltage level that is at least about equal to, and preferably greater than, an external power supply voltage. The signals generated by these signal generators can thus be used by operating voltages which are much less than was previously possible.

Sense amplifier circuit in semiconductor memory device

A voltage boosting circuit for a semiconductor memory device has a clock generator for supplying a chip master clock determining an active state and a stand-by state in respective response to first and second states thereof, for generating a detector control signal a first delay time after the first state of the chip master clock is generated, and for generating a latch control signal a second delay time after the first state of the chip master clock is generated. A boosting voltage detector responds to the detector control signal and the latch control signal to generate a detecting signal indicative of a current state of a boosting voltage potential. First and second boosting voltage generators generate the boosting voltage potential, respectively operating in the stand-by state and active state in accordance with the detecting signal and delayed chip master clock signal.

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Seoul, South Korea

Sei-seung Yoon