Cree Gmbh

Wolfspeed, Inc.

Auburn University

Cree Research Inc.

Sei-Hyung Ryu

Anant Kumar Agarwal

Qingchun Zhang

Daniel Jenner Lichtenwalner

John Williams Palmour

Woongsun Kim

Naeem Islam

Jason Patrick Henning

Scott Thomas Allen

Sarit Dhar

Mrinal Kanti Das

Lin Cheng

Kijeong Han

Edward Robert Van Brunt

Ranbir Singh

Charlotte Jonas

Thomas E Harrington, Iii

Adam Barkley

Brett Hull

Hudson McDonald Hobgood

Jason Ronald Jenny

Craig Capell

Allen Hefner

Matthew Donofrio

Joseph John Sumakeris

Joe W McPherson

Sarah Kay Haney

Jason Gurganus

James Theodore Richmond

Doyle Craig Capell

Sumithra Krishnaswami

Joohyung Kim

Madankumar Sampath

Arman Ur Rashid

Zoltan Ring

Daniel Namishia

Robert J Callanan

Lori A Lipkin

Allan Ward

Zachary Cole

Marcelo Schupbach

John Robert Williams

Matt N McCain

Rahul R Potera

Matthew N McCain

Erik Maki

Kraig J Olejniczak

Edward Harold Hurt

D Craig Capell

David Grider

Marcelo Schupback

Matt Donofrio

A method of forming ohmic contacts on a semiconductor structure having a p-type region and an n-type region includes depositing a first metal on the n-type region, annealing the structure at a first contact anneal temperature to form a first ohmic contact on the n-type region, depositing a second metal on the first ohmic contact and on the p-type region, and annealing the structure at a second contact anneal temperature, less than the first contact anneal temperature, to form a second ohmic contact on the p-type region.

Methods of forming ohmic contacts on semiconductor devices with trench/mesa structures

Power semiconductor devices include a semiconductor layer structure comprising an active area with a plurality of unit cell transistors and an inactive gate pad area, a gate resistor layer on an upper side of the semiconductor layer structure, an inner contact that is directly on the upper side of the gate resistor layer, and an outer contact that is directly on the upper side of the gate resistor layer. The outer contact encloses the inner contact within the inactive gate pad area of the semiconductor device.

Semiconductor devices having gate resistors with low variation in resistance values

A vertical semiconductor and method for fabricating the same is disclosed. In one embodiment, fabrication entails providing a precursor comprising a substrate and a drift region over the substrate. A plurality of trenches is etched into the drift region from a top surface of the drift region such that a plurality of mesas remains in an upper portion of the drift region. The plurality of trenches is then filled with a first material. A vertical semiconductor device includes a plurality of mesas extends from an upper portion of the drift region, wherein there are no regrowth interfaces between the drift region and the plurality of mesas. A first material fills the trenches between each one of the plurality of mesas. At least one first contact over at least one of the plurality of mesas. At least one second contact over a bottom surface of the substrate.

Vertical power devices having mesas and etched trenches therebetween

A power semiconductor device includes a semiconductor layer structure comprising a drift region of a first conductivity type, and a gate trench extending into the drift region. The gate trench includes sidewalls and a bottom surface therebetween. A bottom shielding structure of a second conductivity type is provided under the bottom surface of the gate trench. First and second support shielding structures of the second conductivity type extend into the drift region on opposing sides of the gate trench and are spaced apart from the sidewalls thereof. A material composition, distance of extension into the drift region relative to a surface of the semiconductor layer structure, and/or dopant concentration of the bottom shielding structure may be different from that of the first and second support shielding structures. Related devices and fabrication methods are also discussed.

Support shield structures for trenched semiconductor devices

A vertical semiconductor device includes a substrate, a drift region over the substrate, an upper region on the drift region, a top surface over the upper region and being substantially planar, and a series of implants of a second dopant in the upper region, such that each implant of the series of implants is located at a different depth below the top surface. The series of implants forms at least two gate region. The substrate and the drift region are doped with a first dopant of a first polarity. The second dopant has a second polarity opposite that of the first polarity. At least a portion of a channel region is provided between the at least two gate regions, and a conducting gap is defined within the channel region and between opposing sidewalls of the at least two gate regions.

Vertical power devices fabricated using implanted methods

Semiconductor devices and methods of forming the devices are provided. Semiconductor devices include a semiconductor layer structure comprising a trench in an upper surface thereof, a dielectric layer in a lower portion of the trench, and a gate electrode in the trench and on the dielectric layer opposite the semiconductor layer structure. The trench may include rounded upper corner and a rounded lower corner. A center portion of a top surface of the dielectric layer may be curved, and the dielectric layer may be on opposed sidewalls of the trench. The dielectric layer may include a bottom dielectric layer on a bottom surface of the trench and on lower portions of the sidewalls of the trench and a gate dielectric layer on upper portions of the sidewalls of the trench and on the bottom dielectric layer.

Power semiconductor devices including a trenched gate and methods of forming such devices

Semiconductor devices and methods of forming a semiconductor device that includes a polysilicon layer that may improve device reliability and/or a functioning of the device. An example device may include a wide band-gap semiconductor layer structure including a drift region that has a first conductivity type; a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a bottom surface, a first sidewall, a second sidewall, and an upper opening; and a plurality of polysilicon layers, each polysilicon layer on the second sidewall of a respective gate trench.

Trench bottom shielding methods and approaches for trenched semiconductor device structures

Semiconductor devices, and in particular protection structures for semiconductor devices that include sensor arrangements are disclosed. A semiconductor device may include a sensor region, for example a current sensor region that occupies a portion of an overall active area of the device. The current sensor region may be configured to provide monitoring of device load currents during operation. Semiconductor devices according to the present disclosure include one or more protection structures that are configured to allow the semiconductor devices to withstand transient voltage events without device failure. A protection structure may include an insulating layer that is provided in a transition region between a device region and the sensor region of the semiconductor device. In the example of an insulated gate semiconductor device, the insulating layer of the protection structure may include a material with a greater breakdown voltage than a breakdown voltage of a gate insulating layer.

Protection structures for semiconductor devices with sensor arrangements

A power semiconductor device includes a semiconductor layer structure comprising a wide bandgap semiconductor material. The semiconductor layer structure includes a drift region of a first conductivity type and a plurality of fin structures protruding from the drift region. The fin structures comprise respective source regions of the first conductivity type and respective channel regions between the respective source regions and the drift region. Related devices and methods are also discussed.

FinFET power semiconductor devices

Semiconductor devices and methods of forming a semiconductor device that includes a deep shielding pattern that may improve a reliability and/or a functioning of the device. An example method may include forming a wide band-gap semiconductor layer structure on a substrate, the semiconductor layer structure including a drift region that has a first conductivity type; forming a plurality of gate trenches in an upper portion of the semiconductor layer structure, the gate trenches spaced apart from each other, each gate trench having a bottom surface, a first sidewall, a second sidewall, and an upper opening; forming an obstruction over a portion of each gate trench that partially obscures the upper opening; and implanting dopants having a second conductivity type that is opposite the first conductivity type into the bottom surfaces of the gate trenches, where the dopants implanted into the bottom surface of the gate trenches form deep shielding patterns.

Sidewall dopant shielding methods and approaches for trenched semiconductor device structures

A vertical semiconductor device includes one or more of a substrate, a buffer layer over the substrate, one or more drift layers over the buffer layer, and a spreading layer over the one or more drift layers.

Vertical semiconductor device with improved ruggedness

A power semiconductor device comprises a semiconductor layer structure comprising a drift region that comprises a wide band-gap semiconductor material that has a first conductivity type, a well region that has a second conductivity type, and a source region that has the first conductivity type in an upper portion of the well region and a gate trench in an upper portion of the semiconductor layer structure and comprising a portion obliquely angled in plan view. Sidewalls of the gate trench may extend along substantially the same crystal plane in the semiconductor layer structure.

Power semiconductor devices including angled gate trenches

Shielding techniques are used to provide an embedded sensor element such as a temperature sensing element on a wide bandgap power semiconductor device. A semiconductor device may include a drift layer and an embedded sensor element. The drift layer may be a wide bandgap semiconductor material. A shielding structure is provided in the drift layer below the embedded sensor element. The embedded sensor element may be provided between contacts that are in electrical contact with the shielding well. The distance between the contacts may be minimized. A noise reduction well may be provided between the contacts to further isolate the embedded sensor element from parasitic signals.

Wide bandgap semiconductor device with sensor element

A power semiconductor device includes semiconductor layer structure comprising a semiconductor drift region of a first conductivity type and an edge termination region comprising a plurality of guard rings of a second conductivity type. The guard rings extend into a surface of the semiconductor drift region. The guard rings respectively comprise a first portion adjacent the surface and a second portion spaced from the surface, where the first portion is wider than the second portion. Related devices and fabrication methods are also discussed.

Edge termination for power semiconductor devices and related fabrication methods

A semiconductor device includes a vertical transistor and a body diode. Various improvements to the semiconductor device allow for improved performance of the body diode, in particular to reduced snappiness and increased softness.

Power transistor with soft recovery body diode

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Cary, NC, United States of America

Sei-Hyung Ryu