Samsung Electronics Co., Ltd.

Sehwan Park

Jihoon Kim

Jinyoung Kim

Youngdeok Seo

Ilhan Park

Dongmin Shin

Youngjoo Park

Sangwan Nam

Jinhee Choi

Minjeong Kang

Hyun Seok Seo

Joonsuc Jang

Wandong Kim

Kyoman Kang

Jisang Lee

Woohyun Kang

Sungmin Joe

Sanghyun Choi

Heewon Lee

Kangho Roh

Seoyoung Lee

Junho Kim

Jaeyong Lee

Jihoon Lee

Sungwook Park

Jongsam Kim

Dongyeol Lee

Jaebeom Byun

Eunhyang Park

Shinho Oh

Younghwi Yang

Heetai Oh

Hyojung Jang

Silwan Chang

Jihoon Lêe

A memory device may include a memory block and a control circuit. The memory block may include a first sub-block and a second sub-block that are connected between a common source line and a plurality of bit lines and may be vertically stacked. The control circuit may be configured to select any one of the common source line and the plurality of bit lines as a transmission path of an erase voltage based on positions of the first sub-block and the second sub-block, and perform erase operations on the first sub-block and the second sub-block in units of sub-blocks.

Memory device that performs erase operation to preserve data reliability

A vertical non-volatile memory device capable of stably maintaining an operating temperature in a chip level, a semiconductor package including the memory device, and a heat dissipation method of the memory device. The vertical non-volatile memory device includes a substrate on which a cell array area and an extension area are defined, a vertical channel structure formed on the substrate, a thermoelectric device including at least two semiconductor pillars formed on the substrate, and a stacked structure on the substrate. The stacked structure includes a gate electrode layer and an interlayer insulation layer which are stacked alternately along sidewalls of the vertical channel structure and the at least two semiconductor pillars. The at least two semiconductor pillars include an n-type semiconductor pillar and a p-type semiconductor pillar which are electrically connected to each other through a conductive layer on the substrate.

Vertical non-volatile memory device including thermoelectric device, semiconductor package including the memory device, and heat dissipation method of the memory device

An operating method of a nonvolatile memory device for programming multi-page data, the operating method including: receiving the multi-page data from a memory controller; programming first page data among the multi-page data to first memory cells connected to a word line adjacent to a selected word line; reading previous page data previously stored in second memory cells connected to the selected word line based on a first sensing value and a second sensing value after programming the first page data; calculating a first fail bit number by comparing first bits of the previous page data read based on the first sensing value to second bits of the previous page data read based on the second sensing value; and programming the previous page data read from the second memory cells and second page data among the multi-page data to the second memory cells based on the first fail bit number.

Operating method of a nonvolatile memory device for programming multi-page data

Aggressor memory cells connected to one or more aggressor wordlines are grouped into aggressor cell groups by performing a read operation with respect to the aggressor wordlines based on one or more grouping read voltages, where the aggressor wordlines are adjacent to a selected wordline corresponding to a read address among wordlines of a memory block. Selected memory cells connected to the selected wordline are grouped into a selected cell groups respectively corresponding to the aggressor cell groups. Group read conditions respectively corresponding to the selected cell groups are determined and group read operations are performed with respect to the plurality of selected cell groups based on the group read conditions. The read errors are reduced by grouping the selected memory cells into the selected cell groups according to the change of operation environments.

Nonvolatile memory device and method of operating the same

A non-volatile memory device includes a memory cell array including a plurality of memory blocks that includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to select one among the plurality of memory blocks, based on an address, a voltage generator configured to apply word line voltages corresponding to selected word lines and unselected word lines, among the plurality of word lines, page buffers connected to the plurality of bit lines and configured to read data from a memory cell connected to one among the selected word lines of the selected one among the plurality of memory blocks, and a control logic configured to control the row decoder, the voltage generator, and the page buffers.

Non-volatile memory device, operating method thereof, controller for controlling the same, and storage device having the same

A method and an apparatus are provided for executing applications. Based on a first user input, a first window including number keys is displayed. Based on a second user input selecting a key, a second window is displayed including a list of applications. Based on an application being selected, the selected application is mapped to the selected key and an icon image corresponding to the selected application is displayed in the selected key. After the selected application is mapped, a third user input is received corresponding to the selected key. In response to the third user input, a function is performed associated with the selected application in case that a duration of the third user input is longer than or equal to a threshold duration, and an operation different from the function is performed in case that the duration is shorter than the threshold duration.

Method and apparatus for providing search function in touch-sensitive device

A controller including a non-volatile memory interface circuit connected to at least one non-volatile memory device and configured to control the at least one non-volatile memory device; an error correction circuit configured to perform an error correction operation on a codeword received from the non-volatile memory interface circuit according to an error correction decoding level from among a plurality of error correction decoding levels, wherein the non-volatile memory interface circuit is further configured to: receive side information from the at least one non-volatile memory device; predict a distribution of memory cells based on the side information; and select the error correction decoding level from among the plurality of error correction decoding levels according to the predicted distribution.

Non-volatile memory device, controller for controlling the same, storage device having the same, and reading method thereof

In a method of reading data in a nonvolatile memory device including a plurality of memory cells having a plurality of states including a first state and a second state, a first read operation for the first state is performed, and a second read operation for the second state is performed. To perform the first read operation, cell counts for a valley of the first state are obtained by performing a valley cell count operation for the first state, a first read voltage level for the first state is determined based on the cell counts and at least one first reference parameter for the first state, and a first sensing operation for the first state is performed by using the first read voltage level. To perform the second read operation, a second read voltage level for the second state is determined based on the cell counts and at least one second reference parameter for the second state, and a second sensing operation for the second state is performed by using the second read voltage level.

Method and device for reading data in a nonvolatile memory device based on cell counts of two states

A nonvolatile memory device includes a memory block including a memory area, an on-chip valley search (OVS) circuit performing an OVS sensing operation on the memory block, and a buffer memory storing at least one variation table including variation information of a threshold voltage of memory cells, obtained from the OVS sensing operation. A reading operation including an OVS sensing operation and a main sensing operation on the memory area is performed in response to a read command applied by a memory controller, the OVS sensing operation is performed at an OVS sensing level, and the main sensing operation is performed at a main sensing level reflecting the variation information. In the nonvolatile memory device, correction accuracy for deterioration of a word line threshold voltage may be improved, and a burden on a memory controller may be reduced.

Nonvolatile memory device, with valley search for threshold voltage, memory controller, and reading method of storage device including the same

A storage device includes a nonvolatile memory device and a memory controller to control the nonvolatile memory device. The nonvolatile memory device includes a memory cell array. The memory cell array includes a normal cell region, a parity cell region and a redundancy cell region. First bit-lines are connected to the normal cell region and the parity cell region and second bit-lines are connected to the redundancy cell region. The memory controller includes an error correction code (ECC) engine to generate parity data. The memory controller stores user data in the normal cell region, controls the nonvolatile memory device to perform a column repair on first defective bit-lines among the first bit-lines, assigns additional column addresses to the first defective bit-lines and the second bit-lines and stores at least a portion of the parity data in a region corresponding to the additionally assigned column addresses.

Storage devices and methods of operating storage devices

Operating method of a nonvolatile memory device for programming multipage data

A method of operating a nonvolatile memory device is provided. The method includes: dividing a memory block of a plurality of memory blocks provided in the nonvolatile memory device into a plurality of retention groups; generating time-difference information including a plurality of erase program interval (EPI) values corresponding to the plurality of retention groups; generating offset information including a plurality of offset values corresponding to differences between a plurality of default read voltages and a plurality of corrected read voltages; generating compensated read voltages corresponding to a read address based on the offset information and the time-difference information; and performing a read operation to read data from the nonvolatile memory device based on the read address and the compensated read voltages.

Storage device including nonvolatile memory device and method of operating the same

A nonvolatile memory device includes; a memory cell array including a meta data region storing chip-level information, control logic identifying a target cell in response to a command, machine learning (ML) logic inferring an optimum parameter based on the chip-level information and physical information associated with the target cell applied as inputs to an artificial neural network model, and a buffer memory configured to store weight parameters of the artificial neural network model.

Nonvolatile memory device including artificial neural network, memory system including same, and operating method of nonvolatile memory device including artificial neural network

Growing community of inventors

Gyeonggi-do, South Korea

Sehwan Park