Marvellworld Trade Ltd.

Marvell International Limited

Marvell Technology Group Ltd.

Flc Technology Group, Inc.

Other

Flc Global, Ltd.

8x8, Inc.

Marvell Semiconductor, Inc.

Integrated Information Technology, Inc.

Ykk Corporation

Marvell Asia Pte., Ltd.

Megic Corporation

8.times.8, Inc.

Marvell World Trade International

Sehat Sutardja

Pantas Sutardja

Farbod Aram

Runsheng He

Jiancheng Zhang

Albert M Wu

Pierte Roo

William Lo

Saeed Azimi

Hong-Yi Chen

Ravishanker Krishnamoorthy

Poh Boon Leong

Winston Lee

Wanfeng Zhang

Brian Taylor Brunn

Eric Janofsky

Hedley Rainnie

Lawrence Tse

Gregory Takeo Uehara

Bryan R Martin

Peter Loc

Jan Fandrianto

Chi S Wang

Jody Greenberg

Peter W Lee

Ping Song

Xiaodong Jin

Jason T Su

Jensen Tjeng

Xiaohua Fan

Jason Sheu

Donald Robert Pannell

Shiann-Ming Liou

Jianqing Lin

Nuntha Kumar Krishnasamy Maniam

Hedley K Rainnie

King Chun Tsai

Huahung Kao

Yat-Tung Lam

Yun Yang

Shuran Wei

Hedley K J Rainnie

Thart Fah Voo

Son Hong Ho

Jinho Choi

Shafiq M Jamal

Po-Chien Chang

Fan Yang

Chuan-Cheng Cheng

Kan Li

Alessandro Venca

Thomas B Cho

Sofjan Goenawan

Roawen Chen

Scott Wu

Ashutosh Verma

Hunglin Hsu

Enrico Sacchi

Leechung Yiu

Rong Xu

Vincent Kao

Hendrick Santo

Xiaojue Zeng

Mou-Shiung Lin

Jin-Yuan Lee

Tsahi Daniel

Mark Norman Fullerton

Siew Yong Chui

Rinaldo Castello

Premanand Sakarda

Hubertus Notohamiprodjo

Chien-Chuan Wei

Long-Ching Wang

Francesco Rezzi

Jay S Heeb

Weidan Li

Dimitry Melts

Giovanni Cesura

Alan Armstrong

Joseph Sheredy

Gani Jusuf

Shuhua Yu

Hong Zhang

Huy Thong Nguyen

Hou Xian Loo

Chung Chyung Han

Hyun Jeong Shin

Gareth Seng Thai Yeo

Justin Heindel

Bo Hu

Cheng Chung Wang

Jianchen Zhang

Wei Ding

Jay Heeb

A data access system including a processor, multiple cache modules for the main memory, and a storage drive. The cache modules include a FLC controller and a main memory cache. The multiple cache modules function as main memory. The processor sends read/write requests (with physical address) to the cache module. The cache module includes two or more stages with each stage including a FLC controller and DRAM (with associated controller). If the first stage FLC module does not include the physical address, the request is forwarded to a second stage FLC module. If the second stage FLC module does not include the physical address, the request is forwarded to the storage drive, a partition reserved for main memory. The first stage FLC module has high speed, lower power operation while the second stage FLC is a low-cost implementation. Multiple FLC modules may connect to the processor in parallel.

Method and apparatus for using a storage system as main memory

A noise tolerant buffer circuit, configured to interface a controller to a switching device, that includes an input, a first buffer, a second buffer, an output, and a switching device. The input provides a control signal to the first buffer cell input. The first buffer cell processes the control signal to generate a second buffer output. The second buffer cell processes the output of the first buffer to generate a second buffer output. The switching device is configured to receive an output of the second buffer and perform a switching operation based on the output of the second buffer. The switching operation generates noise that couples back to the first buffer cell and the second buffer cell, and the noise is divided between the first buffer cell and a second buffer to thereby reduce the noise to a value that does not trigger the first buffer or the second buffer.

Noise tolerant buffer

A latch for a flip-flop or other circuit which requires fewer signal inputs than prior latch designs to reduce power consumption. The latch comprises a first transistor set is switching element and is configured to receive clock signals from a clock network and an input signal. A second transistor receives the input signal from the first transistor set and is configured as a first data buffer to create a latch output. A feedback path includes a third transistor set in series with a resistor or transistor pair. The feedback path receives the latch output and generates a feedback signal, which is provided to the first transistor set. The resistor or transistor pair is selected to establish the feedback signal at a magnitude that is sufficiently large to maintain the state of the latch but sufficiently small to allow a change in the input signal to change the latch output.

Ultra-low power D flip-flop with reduced clock load

To avoid hash table collisions, such as in response to sequential addresses, a hash module is provided that includes a first multiplexer that, responsive to a control signal, outputs received data on one of two or more scramblers. The scramblers are configured to selectively receive the selected data output from the first multiplexer and perform a scrambler operation on the selected data to generate scrambled data. A second multiplexer outputs the scrambled data to a first hash module configured to performs a hash function on the scrambled data to generate a hash value. A second hash module, responsive to a collision occurring in the first hash module, perform a hash function on the scrambled data received from the first hash module. The use of a scrambler reduces collisions in the hash module outputs over time and multiple scramblers may be used to further reduce collisions.

Hash function with pre-scrambler

A transformer comprising a primary winding and a secondary winding. The primary winding has Nnumber turns and having a first terminal and a second terminal. The secondary winding has having Nfractional portions, which together form a full turn, are in close proximity to the primary winding to establish coupling between the primary winding and the Nfractional coil portions, the transformer turn ratio from the primary winding to the secondary winding is N:(N/N) where Nis an integer equal to or greater than 1, Nis an integer greater than or equal to 2, and Nis an integer greater than or equal to 1. Also disclosed is a stacked integrated transformer having a primary winding and secondary winding of which one or both have a waterfall structure and a portion of which functions as a ground connected shield between the secondary winding and the primary winding.

Fractional transformer

Transformer structure

A data access system including a processor and a storage system including a main memory and a cache module. The cache module includes a FLC controller and a cache. The cache is configured as a FLC to be accessed prior to accessing the main memory. The processor is coupled to levels of cache separate from the FLC. The processor generates, in response to data required by the processor not being in the levels of cache, a physical address corresponding to a physical location in the storage system. The FLC controller generates a virtual address based on the physical address. The virtual address corresponds to a physical location within the FLC or the main memory. The cache module causes, in response to the virtual address not corresponding to the physical location within the FLC, the data required by the processor to be retrieved from the main memory.

Storage system and method for accessing same

A system and method for caching memory request verification data comprising a memory request generator configured to generate a memory request designating requested data and memory request verification data. A bus is configured to carry the memory request from the memory request generator to a cache memory that stores verification data, and upon receiving the memory request is configured to: retrieve stored verification data from the cache memory, compare the stored verification data to the memory request verification data, and responsive to a match between the stored verification data to the memory request verification data, designate a memory request validation. Also part of the system is a memory controller configured to, responsive to a memory request validation, retrieve data specified in the memory request from a main memory and provide the data to the memory request generator over the bus. A main memory configured to store the requested data.

Method and apparatus for caching MTE and/or ECC data

A system includes a read/write module and a caching module. The read/write module is configured to access a first portion of a recording surface of a rotating storage device. Data is stored on the first portion of the recording surface of the rotating storage device at a first density. The caching module is configured to cache data on a second portion of the recording surface of the rotating storage device at a second density. The second portion of the recording surface of the rotating storage device is separate from the first portion of the recording surface of the rotating storage device. The second density is less than the first density.

Method and apparatus for caching data in an solid state disk (SSD) of a hybrid drive that includes the SSD and a hard disk drive (HDD)

Method and apparatus for accessing data stored in a storage system that includes both a final level of cache and a main memory

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Los Altos Hills, CA, United States of America

Sehat Sutardja