Lg Display Co., Ltd.

Seeung Lee

Chansoo Park

Seungseok Ryoo

MinJic Lee

Byunghyun Lee

Haye Kim

Jongbeom Lee

HyungBeom Shin

SeongHun Jeong

Hanna Choi

A gate driving circuit includes a plurality of stages connected to one another, wherein each of the plurality of stages includes an output unit which outputs a first clock signal as a gate voltage in accordance with a voltage of a Q node and a voltage of a QB node; a first node control unit which controls the voltage of the Q node; and a second node control unit which controls the QB node, wherein the first node control unit includes second and third transistors which discharge the Q node, the second transistor outputs a ground voltage to the Q node in response to a second clock signal, and the third transistor outputs the ground voltage to the Q node in response to the voltage of the QB node.

Gate driving circuit and display device including the same

Provided is a display device. The display device includes a substrate including an active area in which a plurality of pixels is disposed and a non-active outside a periphery of the active area. A plurality of signal lines is disposed in parallel with one another and extend in a first direction in the non-active area. Each of the plurality of signal lines includes a first portion, a second portion, and a third portion which are sequentially connected to one another. The first and third portions extend in the first direction and are disposed in parallel with one another. Embodiments provided herein facilitate a reduction of electromagnetic interference between the display device and an external electronic device.

Display device for reducing an electromagnetic interference

A gate driving circuit includes a plurality of stages sequentially connected to one another. The plurality of stages each includes an output unit for outputting a first clock signal as a gate output voltage in response to a voltage of a Q node and a voltage of a QB node; a first node controller configured to charge the voltage of the Q node in response to the gate output voltage from a previous stage; a second node controller configured to charge the voltage of the QB node in response to a second clock signal having a different phase from the first clock signal; a first node stabilizer configured to block a leakage current path of the Q node when the second clock signal is not applied; and a second node stabilizer configured to block a leakage current path of the QB node when the second clock signal is not applied.

Gate driving circuit and display device comprising the same

A liquid crystal display and a method for manufacturing the same capable of reducing a bezel are disclosed. The liquid crystal display includes a display panel including vertical lines, horizontal lines, and pixels and a driver integrated circuit (IC) supplying a data voltage and a gate pulse to the pixels through the vertical lines. The vertical lines include vertical data lines to which the data voltage is supplied, vertical gate lines to which the gate pulse is supplied, and vertical common voltage lines to which a common voltage is supplied. The horizontal lines include horizontal gate lines which are connected to the vertical gate lines and receive the gate pulse through the vertical gate lines.

Liquid crystal display and method for manufacturing the same

A gate driving circuit and a display device using the same are provided. The gate driving circuit includes a first gate driving circuit configured to sequentially generate first and second output voltages and a second gate driving circuit configured to sequentially generate first and second output voltages. The first gate driving circuit and the second gate driving circuit are asymmetrically connected to gate lines. The first output voltage of the first gate driving circuit is supplied to an nth gate line, and the second output voltage of the second gate driving circuit is supplied to the nth gate line.

Gate driving circuit controlling a plurality of transistors with one Q node and display device using the same

A display device is disclosed. The display device includes a substrate having an active area including a plurality of pixels, a bezel area positioned outside the active area, and at least one opening area positioned inside the active area, at least one opening positioned in the opening area, first signal lines arranged in a first direction and making a detour around the opening in the opening area, and second signal lines arranged in a second direction and making a detour around the opening in the opening area. The opening area includes a first opening area in which the first signal lines are arranged and which is adjacent to the opening, and a second opening area in which the second signal lines intersecting the first signal lines are arranged and which is spaced from the opening.

Display device with signal lines detouring around opening inside display area

A display device includes a display panel having vertical lines and horizontal lines formed thereon; sub-pixels; and a driver supplying a data signal and a scan signal to the sub-pixels through the vertical lines and horizontal lines, the vertical lines include a vertical data line to which the data signal is supplied and a vertical scan line to which the scan signal is supplied, the horizontal lines are connected to the vertical scan line and include a horizontal scan line transferring the scan signal in a horizontal direction, and the display panel include a shield electrode for shielding a signal interference between the pixel electrode and the vertical scan line.

Display device

A free-form display is disclosed which makes a step-like pattern adjacent to a free-form portion less visible. The free-form display has an active area and a bezel area, and at least part of a boundary between the active area and the bezel area has a free-form portion. The free-form portion comprises subpixel electrodes and a light blocking portion. A plurality of subpixel electrodes are placed in areas defined by a plurality of gate lines and a plurality of data lines that intersect each other. A light blocking portion has openings exposing the subpixel electrodes, respectively, and is arranged to overlap the gate lines and the data lines. The active area comprises subpixel areas where the subpixel electrodes are placed, and a non-pixel area where no subpixel electrodes are placed. The openings of the light blocking portion adjacent to the non-pixel area, are made in different sizes.

Free-form display

Touch sensor integrated type display device improving touch sensibility. The touch sensor integrated type display device includes a plurality of gate lines and data lines configured to cross over each other, a plurality of thin film transistors disposed at crossings of the gate lines and the data lines, a plurality of pixel electrodes configured to be respectively connected to the thin film transistors and disposed between the data lines so that each of the gate lines crosses over pixel electrodes disposed on a same line, a plurality of touch electrodes configured to overlap the gate lines and the data lines without contacting and overlapping the pixel electrodes, a plurality of touch routing wires configured to be respectively connected to the touch electrodes and arranged in parallel with each other, and a common electrode configured to overlap the data lines, the gate lines, the pixel electrodes and the touch electrodes.

Growing community of inventors

Bucheon-si, South Korea

Seeung Lee