Ansys, Inc.

Seema Naswa

Renuka Vanukuri

Paul Traynar

Praveen Singhal

Example systems and methods are disclosed for estimating wire capacitance in an RTL circuit design. In an embodiment, a reference post-layout design is received from a non-transitory storage medium, and gate-level nets within the reference post-layout design are classified as either long nets or short nets based, at least in part, on an average fanout length within the gate-level net. A parasitic model may be generated for each of the gate-level nets, and the gate-level nets and associated parasitic models may be stored within either a long net database or a short net database based on the classification of the gate-level net. A net from the RTL circuit design may be classified as either long or short based, at least in part, on a number of modules crossed by one or more fanouts within the net. If the net from the RTL circuit design is classified as long, then capacitance for the net may be estimated using a parasitic model selected from the long net database. If the net from the RTL circuit design is classified as short, then capacitance for the net may be estimated using a parasitic model selected from the short net database.

Systems and methods for estimating wire capacitance in a register-transfer level circuit design

Example systems and methods are disclosed for estimating power consumption by a clock tree in a register-transfer level (RTL) circuit design based on a previously generated reference gate-level circuit design. A plurality of regions within the clock tree structure of the reference gate-level circuit design are identified, where the plurality of regions are demarcated by one or more clock gating structures. A region-based clock model is generated that includes at least one clock constraint model for each identified region. The region-based clock model is used to synthesize the clock tree in the RTL circuit design for estimating power consumption.

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Noida, India

Seema Naswa