Lsi Logic Corporation

Nxp B.v.

Nxp Usa, Inc.

See-Hoi Caesar Wong

Edward W Liu

Jean CauXuan Le

Carmelo Morello

Ronak Prakashchandra Trivedi

Ranga Seshu Paladugu

Tae-Song Chung

Hanqing Xing

A method for self-calibration of reference voltage drop in a Digital to Analog Converter (DAC) includes measuring each one of a plurality of thermometric weightages associated with a respective one of a plurality of thermometric bits, wherein the DAC includes a plurality of sub-binary bits and the plurality of thermometric bits. For each sequentially increasing combination of thermometric bit settings including at least two thermometric bits coupled to a high reference voltage and each sub-binary bit coupled to a low reference voltage, performing the steps of: determining a respective combined weightage correction; adding the combined weightage correction to the highest order bit of the combination of thermometric bit settings; and incrementing a number of bits of the combination of thermometric bit settings in response to the number of bits of the sequential combination being less than a total number of the plurality of thermometric bits.

Self-calibration of reference voltage drop in digital to analog converter

One example discloses a reconfigurable analog to digital converter (ADC) device, including: an analog front end (AFE) configured to receive a set of analog input signals and generate a corresponding set of digital output signals; wherein the AFE includes a set of reconfigurable ADC conversion circuits; and a sequencer coupled to the AFE and configured to control the set of reconfigurable ADC conversion circuits with a first AFE channel configuration at a first time and a second AFE channel configuration at a second time.

Reconfigurable analog to digital converter (ADC)

A method and apparatus for optimizing crossover voltage for differential pair switches in a current-steering digital-to-analog converter or the like are disclosed. An array of at least one or more MOSFET switches may be utilized to control the crossover voltage of a differential pair of transistors such that the off time overlap of the differential pair transistors is optimized. In one embodiment, the pull-up and pull-down times of the input for the differential pair transistors are optimized such that the differential pair transistors are not turned off simultaneously. The array of switches may be n-channel MOSFETs when the differential pair are p-channel MOSFETs. Likewise, the array of switches may be p-channel MOSFETs when the differential pair are n-channel MOSFETs. The output of the diflerential pair is free of crossover glitches and is capable of being utilized in a data converter such as a current-steering digital-to-analog converter (DAC).

Method and apparatus for optimizing crossover voltage for differential pair switches in a current-steering digital-to-analog converter or the like

The present invention provides for a shielded capacitor in a digital CMOS fabrication process. The shield capacitor comprises a first surface (also known as a top plate) and a second surface (the bottom plate). The bottom plate has two portions which are connected, and the two portions of the bottom plate are positioned to sandwich the top plate in between the portions. A polysilicon layer is fabricated between the plates and the substrate of the semiconductor to isolate the plates from the substrate. To build the shielded capacitor, the polysilicon layer is fabricated first, then the plates are built on top of the polysilicon layer. The polysilicon layer is silicized and is often connected to the ground.

Capacitors with silicized polysilicon shielding in digital CMOS process

A novel signal processing scheme comprises a digital to analog converter which is clocked at a first frequency, and a switched capacitor filter which receives input from the digital to analog converter and is clocked at a second frequency which is a multiple N times the first frequency. A preferred version of the present invention further comprises an analog signal sychronization circuit which allows the switched capacitor filter to oversample output from the digital to analog converter. The analog signal sychronization circuit comprises a sample and hold circuit, which receives input from the digital to analog converter and holds the input so that the switched capacitor filter can sample the same input N times, and a digital clock generator, which clocks the sample and hold circuit such that the sample and hold circuit only samples settled and valid output data from the digital to analog converter. An RC active filter receives input from the switched capacitor filter and rejects signal images at the first and higher frequencies.

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Fremont, CA, United States of America

See-Hoi Caesar Wong