Stmicroelectronics S.a.

Sgs-thomson Microelectronics S.a.

Other

Sebastien Zink

David Naura

Bruno Leconte

Paola Cavaleri

Jean Devin

Jean-Francedillaois Leon

Bertrand Bertrand

Francois Maugain

The present invention relates to a memory on a silicon microchip, having a serial input/output, an integrated memory array addressable under N bits, and at least one register that is read accessible, after applying a command for reading the register to the memory. The memory stores a most significant address allocated to the memory within an extended memory array wherein the memory is incorporated or intended to be incorporated. A master memory signal is generated based on the most significant address allocated to the memory. A central processing unit executes a command for reading the register and supplies the content of the register to the serial input/output of the memory only if the memory is the master memory within the extended memory array. The memory includes slave memories whose operation depends upon the read/write status of the master memory.

Serial memory comprising means for protecting an extended memory array during a write operation

The present invention relates to a memory on a silicon microchip, comprising a serial input/output and an integrated memory array addressable under N bits. According to the present invention, the memory comprises means for storing a most significant address allocated to the memory within an extended memory array addressable with an extended address of N+K bits, an extended address counter for storing an extended address received at the serial input/output of the memory, the extended address comprising N least significant bits that are applied to the integrated memory array, and K most significant bits, means for comparing the K most significant bits with the most significant address allocated to the memory, and means for preventing the execution of a command for reading or writing the integrated memory array if the K most significant address bits are different to the most significant address allocated to the memory. In one embodiment, a ready/busy pad is provided that is taken to a selected potential to prevent access to the memory.

Method and apparatus for a continuous read command in an extended memory array

An address decoder selectively applies to word lines of a memory array individual signals of variable polarity, negative or positive, the value of which varies according to a word line address applied to the decoder. The decoder comprises a group decoder delivering signals for selecting a group of word lines of variable polarity, at least one subgroup decoder delivering signals for selecting a subgroup of word lines of variable polarity, and word line drivers each comprising means for multiplexing the group and subgroup selection signals, for selecting and selectively applying one of these signals to a word line. Advantages: reduction in the size of the terminating elements of the decoders in relation with the reduction of the technological pitch in Flash memories.

Negative voltage word line decoder, having compact terminating elements

The present invention relates to a method for controlling and for refreshing memory cells in an electrically erasable and programmable memory comprising a memory array organized in sectors, each sector comprising memory cells linked to bit lines and to word lines. The method comprises controlling and refreshing memory cells of pages of the memory array the address of which is indicated by a control and refresh counter comprising data forming tokens usable once. According to the present invention, a control and refresh counter is integrated into each sector of the memory and comprises memory cells linked to the bit lines of the sector. A counter of a sector is erased after reaching a maximum counting value that is chosen so that, when this maximum counting value is reached, memory cells of the counter have undergone a number of electrical stress cycles that is at the most equal to a determined number. Application to Flash memories.

Sectored flash memory comprising means for controlling and for refreshing memory cells

An electrically erasable and programmable memory includes memory cells and a verify-program device. The memory also includes an erase verify device arranged for supplying an erase verify signal having a determined value when a datum read in a memory cell during a first verify-program cycle has an erase logic value. Application particularly to performing a blank verify test in serial input/output Flash memories.

Flash memory comprising an erase verify algorithm integrated into a programming algorithm

A FLASH memory erasable by page includes a flash memory array containing a plurality of floating gate transistors arranged in pages, and a checking circuit for checking the threshold voltages of the floating gate transistors. Programmed transistors that have a threshold voltage less than a given threshold are reprogrammed. The checking circuit includes a non-volatile counter formed by at least one row of floating gate transistors, a reading circuit for reading the address of a page to be checked in the counter, and an incrementing circuit for incrementing the counter after a page has been checked.

Flash memory including means of checking memory cell threshold voltages

A method of writing in page mode in an electrically erasable and programmable non-volatile memory includes an initialization phase of writing an information element for the selection of the page in a storage latch associated with a column of the non-volatile memory array, and the writing in a temporary memory of each of the data bits to be written in the page. A write phase includes the selection of rows of the non-volatile memory array according to the contents of the temporary memory. A page mode write circuit includes one latch per column of the non-volatile memory array to contain a page selection information element, and a control logic circuit to give the row selection signals as a function of the contents of the temporary memory in a phase for writing the column of the non-volatile memory array.

Method for page mode writing in an electrically erasable/programmable non-volatile memory and corresponding architecture

A device and method for the reading of cells of an EEPROM is provided. The device includes at least one reference cell and one circuit for comparison between a current flowing into the reference cell and a current flowing in a cell selected in read mode. The reference cell is in a programmed state. The programming of the reference cell is done after the control reading and during the integrated circuit power-on reset phase, activated by the powering on of the integrated circuit.

Device and method for the reading of EEPROM cells

Disclosed is a device for protection of stored data comprising protection means to control a signal to enable the programming of a memory, the programming being permitted when the enabling signal is in a first state and prohibited when the enabling signal is in a second state, the protection means including a supply voltage drop detection device to set the enabling signal in the second state when the supply voltage is below a threshold, said device further comprising a time delay circuit capable of setting the enabling signal in the second state during a given period when a control signal goes into a first state.

Device for the protection of stored data using a time delay circuit

A device for the resetting of a memory circuit in integrated circuit form includes means to recognize a particular sequence on one or more external signals applied to the integrated circuit, different from the sequences of operational functioning of the integrated circuit.

Externally controlled power on reset device for non-volatile memory in

A method for performing a first programming operation on a non-volatile memory device of the type that is normally programmed by executing a pre-programming erasure algorithm and then a programming algorithm. According to the method, a non-volatile memory device is manufactured with all its memory cells in the same state, and the first programming operation for setting the memory cells to desired states is performed by executing only the programming algorithm. In a preferred method, the memory device is provided with two modes of operation: a first mode in which programming is accomplished by executing the pre-programming erasure algorithm and then the programming algorithm, and a second mode in which programming is accomplished by executing only the programming algorithm. In the preferred method, the memory device is placed in the second mode of operation before the first programming operation is performed. A non-volatile memory device having two modes of operation is also provided.

Non-volatile memory device and method for the programming of the same

A parallel type of memory is divided into P sub-arrays with which there are associated column and row decoding circuits and read circuits. Circuits are used to produce and give P addresses simultaneously to the decoding circuits on the basis of a given address so as to enable the simultaneous reading of P words from a single address. Circuits receive the P information elements extracted from the P words and give them in series at an output port at a frequency greater than the reading frequency. Thus the access time to the information elements seen from the exterior of the memory is reduced.

Parallel-access memory and method

A non-volatile electrically erasable and programmable memory provides both a SDP (software data protection) function and an OTP (one-time protection) function. The memory comprises a memory array having a plurality of memory cells each for storing an information bit. The memory further comprises at least one supplementary cell for storing a first state bit pertaining to the write-accessible (or non-write accessible) state of all the memory cells of the memory array, and at least one other supplementary cell for storing a second state bit relating to the blank state (or non-blank state) of a group of memory cells designed to be programmed only once by the user. A common management circuit for the SDP and OTP cells is located outside the memory array.

Non-volatile electrically erasable and programmable memory

A method for the generation of voltage for the programming or erasure of a non-volatile memory cell is disclosed. Also disclosed is a circuit and a computer readable medium which implement the method. During an operation of programming or erasure in the memory, the slope P of the write voltage ramp is adapted to the number of memory cells to be programmed or erased simultaneously during this operation. This method is particularly useful in the field of non-volatile, electrically erasable and programmable memories.

Growing community of inventors

Aix en Provence, France

Sebastien Zink