Arm Limited

Sebastien Nicolas Ricavy

Nicolaas Klarinus Johannes Van Winkelhoff

Vincent Philippe Schuppe

Christophe Denis Lucien Frey

Denis René André Dufourt

Gerald Jean Louis Gouya

An integrated circuit and method includes retention voltage generation circuitry which receives a supply voltage from a supply voltage node and provides a retention voltage. Functional circuitry is connected between the retention voltage node and a reference voltage node and is held in a data retention state when at least a minimum voltage is provided between the retention voltage node and the reference voltage node. Each of the circuits includes at least one p-type threshold device and at least one n-type threshold device, both having a characteristic threshold voltage. The p-type and n-type threshold devices are connected in parallel between the supply voltage node and the retention voltage node. A variation in the characteristic threshold voltage of either of the at least one p-type or the at least one n-type device maintains at least the minimum voltage between the retention voltage node and the reference voltage node.

Retention voltage generation

A timing circuit and corresponding method are provided to generate an output timing signal in dependence on an input timing signal. The timing circuit comprises a plurality of circuit components, each circuit component configured to receive an input dependent on the input timing signal and to generate an output in dependence on that input. Each circuit component performs switching operations by switching its output level in response to a transition of its input level. Each circuit component exhibits a delay in switching its output level, the delay comprising a first delay associated with a first switching of its output level and a second delay associated with a second switching of its output level. The first switching is in an opposite direction to the second switching and the first delay and the second delay exhibit a change in magnitude as each circuit component repeatedly performs its switching operations. This change in magnitude is in opposite directions for the first delay and the second delay respectively, and the plurality of circuit components are arranged such that a timing of the output timing signal is dependent on both said first delay and said second delay, such that the effects of each on the timing of the output signal counteract one another.

Timing circuit and method of generating an output timing signal

A memory device and method of operation are provided. The memory device comprises a plurality of memory cells arranged in at least one column, during a write operation a data value being written to an addressed memory cell within a selected column from said at least one column. A supply voltage line is associated with each column, the supply voltage line being connectable to a first voltage source to provide a supply voltage at a first voltage level to the associated column. Threshold circuitry is connected to a second voltage source having a second voltage level, the threshold circuitry having a threshold voltage. Control circuitry is used during the write operation to disconnect the supply voltage line for the selected column from the first voltage source, and to connect the threshold circuitry to the supply voltage line for the selected column. As a result, the supply voltage to the addressed memory cell transitions to an intermediate voltage level determined by the threshold voltage of the threshold circuitry, thereby de-stabilizing the addressed memory cell and assisting in the write operation. The technique of the present invention provides a particularly simple and power efficient technique for implementing a write assist mechanism.

Memory device and method of operating such a memory device

Sensing circuitry and a method of operating such sensing circuitry are provided. The sensing circuitry has voltage change detection circuitry for detecting a change in voltage on at least one input line and for producing at least one output signal indicative of that change during a sensing stage of operation. The voltage change detection circuitry comprises at least one latch transistor having a body region insulated from a substrate. Further, body biasing circuitry is provided which, prior to the sensing stage of operation, causes a voltage to be applied to the body region that is derived from the voltage on one of said at least one input lines. Then, during the sensing stage of operation, the body biasing circuitry causes the voltage of the body region to float. Such an arrangement enables removal of the history effect that can sometime affect such latch transistors, whilst alleviating power consumption and noise issues that can occur in certain known sensing circuits.

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Saint Martin d'Heres, France

Sebastien Nicolas Ricavy