Stmicroelectronics (crolles 2) Sas

Commissariat a L'energie Atomique Et Aux Energies Alternatives

Stmicroelectronics S.a.

Stmicroelectronics (rousset) Sas

Sebastien Lagrasta

Raul Andres Bianchi

Simon Jeannot

Sebastien Barnola

Fausto Piazza

Jean-Pierre Oddou

Delia Ristoiu

Cécile Jenny

Christelle Boixaderas

Yann Canvel

Nicolas Posseme

Christian Arvet

The disclosure concerns an electronic component manufacturing method including a first step of etching at least one first layer followed, with no exposure to oxygen, by a second step of passivating the first layer.

Electronic component manufacturing method

An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.

Integrated circuit and method of manufacturing the same

A semiconductor substrate includes a photodiode region, a charge storage region electrically coupled to the photodiode region and a capacitive deep trench isolation (CDTI) structure including a conductive region positioned between the photodiode region and the charge storage region. A contact etch stop layer overlies the semiconductor substrate and a premetallization dielectric layer overlies the contact etch stop layer. A first trench, filled with a metal material, extends through the premetallization dielectric layer and bottoms out at or in the contact etch stop layer. A second trench, also filled with the metal material, extends through the premetallization dielectric layer and the contact etch stop layer and bottoms out at or in the conductive region of the CDTI structure. The metal filled first trench forms an optical shield between the photodiode region and the charge storage region. The metal filled second trench forms a contact for biasing the CDTI structure.

Metal shield trenches and metal substrate contacts supported within the premetallization dielectric (PMD) layer of an integrated circuit using a middle end of line (MEOL) process

The production of spacers at flanks of a transistor gate, including a step of forming a dielectric layer covering the gate and a peripheral region of a layer of semiconductor material surrounding the gate, including forming a superficial layer covering the gate and the peripheral region; partially removing the superficial layer configured so as to completely remove the superficial layer at the peripheral region while preserving a residual part of the superficial layer at the flanks; and selective etching of the dielectric layer vis-&#xe0;-vis the material of the residual part of the superficial layer and vis-&#xe0;-vis the semiconductor material.

Production of spacers at flanks of a transistor gate

Growing community of inventors

La Terrasse, France

Sebastien Lagrasta