Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Stmicroelectronics (crolles 2) Sas

Applied Materials, Inc.

Centre National De La Recherche Scientifique

Stmicroelectronics S.a.

Sebastien Barnola

Nicolas Posseme

Jerome Belledent

Sebastien Lagrasta

Stefan Landis

Lamia Nouri

Laurent Pain

Christian Arvet

Thibaut David

Yann Canvel

Christelle Boixaderas

Srinivas D Nemani

Laurent Grenouillet

Olivier Joubert

Francois Andrieu

Laurent J Vallier

Marie-Anne Jaud

Jerome Mazurier

The disclosure concerns an electronic component manufacturing method including a first step of etching at least one first layer followed, with no exposure to oxygen, by a second step of passivating the first layer.

Electronic component manufacturing method

A method for etching a dielectric layer covering at least one top and at least one flank of a semi-conductive material-based structure is provided, including a plurality of sequences, each including successive steps of: a first etching of the layer by plasma using a chemistry including at least a first fluorine-based compound and a second compound chosen from SiCland SiF, w, x, y, and z being whole numbers, and oxygen, the first etching: interrupting before complete consumption of the dielectric layer thickness on the flank and after complete consumption of the thickness on the top, and forming a first protective layer on the top and a second protective layer on the flank; and a second etching fully removing the second layer while conserving a portion of the first layer thickness, each sequence being repeated until complete removal of the dielectric layer on the flank.

Method of etching a three-dimensional dielectric layer

There is provided a method for producing on a same substrate at least one first transistor and at least one second transistor that have different characteristics, the method including producing at least one first gate pattern and at least one second gate pattern on the substrate; depositing, on the first and the second gate patterns, at least: a first protective layer, and a second protective layer overlying the first protective layer and made of a material different from that of the first protective layer; masking of the second gate pattern by a masking layer; isotropic etching of the second protective layer; removing the masking layer; and anisotropic etching of the second protective layer selectively relative to the first protective layer.

Method for producing on the same transistors substrate having different characteristics

The invention relates to a method of etching a layer of porous dielectric material, characterized in that the etching is performed in a plasma formed from at least one silicon-based gas mixed with oxygen (O) and/or nitrogen (N) so as to grow a passivation layer all along said etching, at least on flanks of the layer of porous dielectric material and wherein the silicon-based gas is taken from all the compounds of the type SiHfor which the ratio x/y is equal or greater than 0.3 or is taken from all the compounds of the following types: SiFand SiCl, where x is the proportion of silicon (Si) in the gas and y is the proportion of fluorine (F) or chlorine (Cl) or hydrogen (H) in the gas.

Method of etching a porous dielectric material

A method for forming reliefs on the surface of a substrate, including a first implantation of ions in the substrate according to a first direction; a second implantation of ions in the substrate according to a second direction that is different from the first direction; at least one of the first and second implantations is carried out through at least one mask having at least one pattern; an etching of areas of the substrate having received by implantation a dose greater than or equal to a threshold, selectively to the areas of the substrate that have not received via implantation a dose greater than said threshold; the parameters of the first and second implantations being adjusted in such a way that only areas of the substrate that have been implanted both during the first implantation and during the second implantation receive a dose greater than or equal to said threshold.

Method for producing patterns by ion implantation

The invention relates in particular to a method for producing subsequent patterns in an underlying layer (), the method comprising at least one step of producing prior patterns in a carbon imprintable layer () on top of the underlying layer (), the production of the prior patterns involving nanoimprinting of the imprintable layer () and leave in place a continuous layer formed by the imprintable layer () and covering the underlying layer (), characterized in that it comprises the following step:

Method for obtaining patterns in a layer

A method for etching a dielectric layer located on the surface of a three-dimensional structure formed on a face of a substrate oriented along a plane of a substrate, which includes a step of implanting ions so as to directionally create a top layer in the dielectric layer. Such top layer is thus not formed everywhere. Then, the layer in question is removed, except on the predefined zones, such as flanks of a transistor gate. A selective etching of the dielectric layer is executed relative to the material of the residual part of the top layer and relative to the material of the face of the substrate.

Method for the surface etching of a three-dimensional structure

A substrate is successively provided with a support (), an electrically insulating layer (), and a semi-conductor material layer (). A first protective mask () completely covers a second area (B) of the semi-conductor material layer and leaves a first area (A) of the semi-conductor material layer uncovered. A second etching mask () partially covers the first area (A) and at least partially covers the second area (B), so as to define and separate a first area and a second area. Lateral spacers are formed on the lateral surfaces of the second etching mask () so as to form a third etching mask. The semi-conductor material layer () is etched by means of the third etching mask so as to form a pattern made from semi-conductor material in the first area (A), the first etching mask () protecting the second area (B).

Method for manufacturing a substrate provided with different active areas and with planar and three-dimensional transistors

The production of spacers at flanks of a transistor gate, including a step of forming a dielectric layer covering the gate and a peripheral region of a layer of semiconductor material surrounding the gate, including forming a superficial layer covering the gate and the peripheral region; partially removing the superficial layer configured so as to completely remove the superficial layer at the peripheral region while preserving a residual part of the superficial layer at the flanks; and selective etching of the dielectric layer vis-&#xe0;-vis the material of the residual part of the superficial layer and vis-&#xe0;-vis the semiconductor material.

Production of spacers at flanks of a transistor gate

Lithography method for etching very dense patterns on a substrate, based on a combination of several less dense partial patterns; a sacrificial layer is formed on a substrate and is etched according to a first partial pattern; spacers are formed on edges of elements of the sacrificial layer, the spacers defining a second partial pattern; then the sacrificial layer is removed leaving only the spacers remaining. A layer sensitive to an electron beam is subsequently deposited between the spacers to a thickness less than or equal to the height of the spacers, and this sensitive layer is exposed using an electron beam according to a third partial pattern such that there remains on the substrate a final pattern of regions lacking spacers and a sensitive layer, this pattern resulting from the combination of the second and third partial patterns and having higher density than each of the partial patterns.

Lithography method for doubled pitch

A method of lithography for formation of two networks of conductors connected by vias in microelectronic integrated circuits comprises, after formation of a first network of buried conductors under an insulating layer: deposition and etching of a sacrificial layer on a substrate, formation of spacers along all edges of elements of the sacrificial layer; removal of this layer; etching of a masking layer. Then, two successive etchings of the insulating layer are carried out, over two successive depths, one defining the depth of the conductors of the second network, the other defining a complement of depth needed at the desired locations for the vias. One of the etchings is defined by the masking layer and corresponds to the locations of the conductors of the second network; the other is defined both by the spacers and by openings in a layer etched by lithography and corresponds to the locations of the vias. Lastly, following the two etchings, the regions etched into the insulating material of the substrate are filled with a conductive material which forms the conductors and the vias at the same time.

Lithographic method for making networks of conductors connected by vias

The substrate is provided with a layer of first material, a first etching mask, a covering layer and a second etching mask. The covering layer has a covered main area and an uncovered secondary area. The secondary area of the covering layer is partially etched via the second etching mask to form a salient pattern. Lateral spacers are formed around the salient pattern defining a third etching mask. The second etching mask is eliminated. The covering layer is etched by means of the third etching mask to form a salient pattern in the covering layer and to uncover the first etching mask and the first material. The layer of first material is etched to form the pattern made from the first material.

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Villard Bonnot, France

Sebastien Barnola