Texas Instruments Corporation

Sebastiano D'Arrigo

Manzur Gill

Michael C Smayling

Sung-Wei Lin

Giuliano Imondi

Sossio Vergara

Giovanni Santin

David J McElroy

Giovanni Naso

Giulio Giuseppe Marotta

Tito Gelsomini

Gerard Chauvel

Gill Manzur

A semiconductor device comprising an integrated circuit and an information unit, said unit being electrically separate from said integrated circuit; an integrated antenna electrically connected with said unit; and an electronic data bank integral with said unit. A method of fabricating an information unit into an integrated circuit chip comprising forming an integrated circuit into a semiconductor substrate using a plurality of process steps; concurrently forming an information unit using a selection of said process steps so that said unit becomes integrated into said chip but remains electrically separate from said integrated circuit; concurrently forming an antenna using a selection of said process steps so that said antenna becomes integrated into said chip and electrically connected to said information unit; providing a data bank within said information unit; and encoding electronic data permanently into said data bank.

Integrated circuit wireless tagging

In accordance with one embodiment of the invention, a nonvolatile memory array is encased in a P-tank, and the P-tank encased in a deep N-tank, the two tanks separating the memory array from the substrate and from the other circuitry of the integrated memory circuit. The deep N-tank allows application of a negative voltage of perhaps -8 V to the P-tank encasing the memory array. Application of that negative voltage permits the cells of the memory array to be programmed with voltage pulses having a peak value of about +10 V, rather than the +18 V peak value of prior-art memory arrays. Because the external circuitry, such as the wordline driver circuit, need drive the wordlines at +10 V rather than +18 V, the invention permits construction of that external circuitry using thinner gate insulators and space-saving shorter dimensions.

Flash EEPROM array with P-tank insulated from substrate by deep N-tank

Interconnection-pin memory comprising an array of dual-port switching memories used as first-in, first-out devices, characterized in that each dual-port memory (3, 4) of the memory array includes a write-only port (15, 23) and a read-only port (18, 19, 20, 21) having separate address and control signals.

Crosspoint memory

A circuit for applying reading, programming and erasing voltages to a wordline in a floating-gate-type EEPROM cell array comprising a positive voltage switching circuit, a first isolating transistor, and a second isolating transistor. The positive voltage switching circuit may include an inverter with feedback transistor and a third isolating transistor. In one embodiment, the positive voltage switching circuit is capable of switching up to three positive voltage values and reference voltage to the wordline terminal.

Wordline driver circuit for EEPROM memory cell

A method is described for programming a semiconductor array of EEPROM cells. A selected cell is connected, by definition, to a selected source-column line, a selected drain-column line and a selected wordline. Each deselected memory cell in the array is connected to a deselected source-column line, a deselected drain-column line and/or a deselected wordline. The method includes preselecting first, second, third, fourth and fifth programming voltages such that the second programming voltage is more positive than the first programming voltage and such that the third, fourth and fifth programming voltages are intermediate between the first and second programming voltages. The first programming voltage is applied at least to a selected column line and to each of the same-type deselected column lines. The third programming voltage is applied to the selected wordline and the fourth programming voltage is applied to each deselected wordline. After a pre-charge time interval, the fifth programming voltage is applied to each same-type deselected column line and, after an optional additional pre-charge time interval, the second programming voltage is applied to the selected wordline. After a program time interval, the third programming voltage is applied to the selected wordline and, after an optional discharge time interval, the first programming voltage is applied to each same-type deselected column line. Each deselected wordline is maintained at the fourth programming voltage for an additional discharge time interval. The third, fourth and fifth programming voltages may have the same value.

Method for programming EEPROM memory arrays

A method is described for programming an array of EEPROM cells. Programming occurs through a Fowler-Nordheim tunnel window (34) between a source bitline (24) and a floating gate conductor (42) of a selected cell. The voltages applied to the control gate and to the source are selected to differ sufficiently to cause electrons to be drawn through the tunnel window (34) from the source region (24) to the floating gate conductor (42). The non-selected bitlines have a voltage impressed thereon that is of sufficient value to prevent inadvertent programming of cells in the selected row. The non-selected wordlines (48) have a voltage impressed thereon that is of sufficient value to prevent erasing of programmed non-selected cells.

Programming of an electrically-erasable, electrically-programmable,

An electrically-erasable, electrically-programmable ROM or an EEPROM is constructed using a floating-gate transistor with or without a split gate. The floating-gate transistor may have a self-aligned tunnel window of sublithographic dimension positioned on the opposite side of the source from the channel and drain, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. In this cell, the bitlines and source/drain regions are buried beneath relatively thick silicon oxide and the floating gate extends over the thick silicon oxide. Programming and erasing are accomplished by causing electrons to tunnel through the oxide in the tunnel window. The tunnel window has a thinner dielectric than the remainder of the oxides under the floating gate to allow Fowler-Nordheim tunneling. Trenches and ditches are used for electrical isolation between individual memory cells, allowing an increase in cell density.

Method of manufacturing an EEPROM with trench-isolated bitlines

A charge-pump circuit implements ramp control, steady-state regulation and trimming of the negative voltage pulses. The circuit includes a negative-voltage charge-pump subcircuit having multiple phase inputs, a phase-enable input, an output, a supply voltage, a reference voltage, a ramp-control subcircuit for controlling the rate of change of the voltage at the output of charge-pump subcircuit, and an amplitude-control subcircuit for controlling the amplitude of the voltage at the output of the charge-pump subcircuit. The ramp-control has an input coupled to the output of the charge-pump subcircuit and an output coupled to the phase-enable input of the charge-pump subcircuit. The amplitude-control subcircuit has an input to the output of the charge-pump subcircuit and has an output coupled to the phase-enable input of the charge-pump subcircuit.

Negative-voltage charge pump with feedback control

An electrically-erasable, programmable ROM cell, or an EEPROM cell, is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small tunnel window, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. The bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ratio of control gate to floating gate capacitance. Programming and erasing are provided by the tunnel window are near or above the channel side of the source. The window has a thinner dielectric than the remainder of the floating gate, to allow Fowler-Nordheim tunneling. By using dedicated drain or ground lines, rather than a virtual-ground layout, and by using thick oxide for isolation between bitlines, the floating gate can extend onto adjacent bitlines and isolation area, resulting in a favorable coupling ratio. Isolation between wordlines is also by thick thermal oxide in a preferred embodiment, further improving the coupling ratio. Bitline and wordline spacing may be selected for optimum pitch or aspect ratio. Bitline to substrate capacitance is minimized.

Fabricating an electrically-erasable, electrically-programmable

A level-shifter circuit includes a deep N-tank to insulate the N-channel portions of transistors from the substrate. The circuit is formed on a P-type substrate coupled to reference voltage Vss. A first field-effect transistor has first and second N+ doped regions formed in a third isolating P- doped region. The third doped region is formed in a fourth isolating N- doped region, which is formed in the substrate. A second transistor has first and second N+ doped regions formed in the same isolation regions as those of the first transistor. A third field-effect transistor has first and second P+ doped regions formed in an isolating N- region that is formed in the substrate. A fourth field-effect transistor has first and second N+ doped regions formed in the same isolation N- region as that of the third transistor. The gate of the first transistor is coupled to a first input. The first doped region of the first transistor is coupled to the output and the second doped region of the first transistor is coupled to the negative voltage Vn. The third doped region is coupled to the negative voltage Vn and the fourth doped region is coupled to the supply voltage Vdd. The second transistor is connected in feedback configuration to the first transistor. The gate of the third transistor is coupled to the second input. The first doped region of the third transistor is coupled to the output and the second doped region of the third transistor is coupled to the voltage Vp, which is more positive than the supply voltage Vdd. The fifth doped region of the third transistor is also coupled to the voltage Vp. The fourth transistor is connected in feedback configuration to the third transistor.

Level-shifter circuit for integrated circuits

An array of nonvolatile memory cells are formed at a face of a semiconductor body, the cells including source regions and including drain regions that are part of a common drain column conductor. Each cell has first and second sub-channel regions between source and drain. The conductivity of the first sub-channel regions of each cell is controlled by a field-plate conductor formed over and insulated from the first sub-channel region. The conductivity of each of the second sub-channel regions is controlled by a floating-gate conductor formed over and insulated from the second sub-channel region. A row line, including control gates, is located above and insulated from the floating gates of the cells for reading, programming and erasing the cells. The field-plate conductor switch provides isolation of the cells during programming.

Nonvolatile memory cell with field-plate switch

First and second EEPROM cells have first and second source regions (28a, 28b) formed in a semiconductor layer (12) to be of a second conductivity type opposite the first conductivity type of the layer and to be spaced apart from each other. A field plate conductor (100) is insulatively disposed adjacent, and defines, an inversion region (102), and further is laterally spaced between the first and second source regions (28a, 28b). The inversion region (102) is inverted from the first conductivity type to the second conductivity type upon application of a predetermined voltage to the field plate conductor (100). First and second channel regions (48a, 48b) are defined between the respective source regions (28a28b) and the inversion region (102) and each include floating gate and control gate subchannel regions (60a, 62a, 62b, 60b). First and second floating gate conductors (40a, 40b) are insulatively disposed adjacent respective floating gate subchannel regions (60a , 60b) to control their conductance. A control gate conductor is insulatively disposed adjacent the control gate subchannel regions (62a, 62b) to control their conductance. In another embodiment, the field plate conductor (100) is replaced with a pair of field plate conductors (42a, 42b) that control the conductance of respective subchannel regions (64a, 64b). The field plate conductors (42a, 42b) act to self-align a diffused drain region (46) that replaces the inversion region (102).

Method of making electrically programmable and erasable memory cells

An electrically-erasable, programmable ROM cell, or an EEPROM cell, is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small tunnel window, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. The bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ration of control gate to floating gate capacitance. Programming and erasure are provided by the tunnel window area, which is located near or above the channel side of the source. The window has a thinner dielectric than the remainder of the floating gate, to allow Fowler-Nordheim tunneling. By using dedicated drain or ground lines, rather than a virtual-ground layout, and by using thick oxide for isolation between bitlines, the floating gate can extend onto adjacent bitlines and isolation area, resulting in a favorable coupling ratio. Isolation between cells in the wordline direction is by a self-aligned implanted region, in this embodiment.

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Houston, TX, United States of America

Sebastiano D'Arrigo