Stmicroelectronics Design and Application Gmbh

Sebastian Zeller

Peter Kirchlechner

Martin Frey

A continuous time sigma-delta analog-to-digital converter comprising: a summator of an input analog signal and a feedback signal; a feed-forward integrator path connected to the summator and configured to provide a digital signal; a feedback digital-to-analog converter to convert the digital signal into a feedback analog signal; a feedback low pass filter structured to filter the feedback analog signal and provide the feedback signal to the summator.

Continuous time sigma-delta A/D converter and electrical system comprising the A/D converter

An image frequency rejection mixer has a first differential transconductor that receives a differential mixer input signal, a second differential transconductor that receives the differential mixer input signal and cross-coupled to the first differential transconductor, a first mixing circuit that generates a first differential mixing circuit output signal by mixing a first differential information signal with a first local oscillation signal, a second mixing circuit that generates a second differential mixing circuit output signal by mixing a second differential information signal with a second local oscillation signal, with the first local oscillation signal and the second local oscillation signal being in quadrature, and an image rejection circuit that generates a differential mixer output signal from the first and second differential mixing circuit output signals.

Image frequency rejection mixer

A harmonic rejection mixer includes a differential in-phase signal path and a differential quadrature signal path, a shared differential transconductor for generating a shared transconductor output signal from a mixer input signal, a first selective mixing circuit disposed in the differential quadrature signal path and coupled to the shared differential transconductor, and a second selective mixing circuit disposed in the differential in-phase signal path and coupled to the shared differential transconductor, the first selective mixing circuit is controlled by a first selective control signal and the second selective mixing circuit is controlled by a second selective control signal to selectively supply the shared transconductor output signal to the differential quadrature signal path and the differential in-phase signal path, respectively.

Harmonic rejection mixer

A loop filter having a first node on which to receive an input signal to the loop filter, a second node on which to provide an output signal of the loop filter, and a cascade arrangement of at least a first circuit that generates a zero, a second circuit that generates a first pole, and a third circuit that generates a second pole to form a passive loop filter of at least 3rd order. The cascade arrangement includes a first signal path coupling the first node to the second node, such that the first circuit is coupled to the first node through the second circuit and the third circuit. Further, the loop filter includes at least one transistor circuit, and a second signal path coupled in parallel to the first signal path at the first node and coupled to the second node through the transistor circuit.

Loop filter

A harmonic rejection mixer for carrying out a frequency translation of a mixer input signal having a mixer input frequency, the mixer including an up-conversion mixer for generating an intermediate signal by multiplying the mixer input signal with a first local oscillation signal having a first local oscillation frequency, and a down-conversion mixer for generating a mixer output signal by multiplying the intermediate signal with a second local oscillation signal having a second local oscillation frequency. The first local oscillation frequency and the second local oscillation frequency are greater than the mixer input frequency. The first local oscillation signal is an l-time oversampled sine wave and the second local oscillation signal is an m-time oversampled sine wave.

A frequency divider having a plurality of programmable latches connected in a feedback shift register configuration. A programmable latch of said plurality of latches comprises a program input to receive a program signal configured to select a polarity of the programmable latch among two opposite polarities. The frequency divider having a configuration module structured to provide at least the program signal to the program input to modify a divisor parameter of the frequency divider.

Programmable frequency divider comprising a shift register and electrical system comprising the frequency divider

A current-controlled resistor comprises a first input terminal configured to receive an input signal and a second input terminal configured to receive a current control signal. The resistor comprises a first stage configured to receive the current control signal; the first stage includes first and second PN diodes having first terminals of a first type and second terminals of a second type. The first terminals of the first and second PN diodes are coupled each other and a second terminal of the first PN diode is coupled to the first input terminal. The resistor comprises a second stage configured to receive the current control signal; the second stage includes a third PN diode having first and second terminals of the first and second types, the second terminal of the third PN diode being coupled to the second terminal of the second PN diode.

Current-controlled resistor

A transconductor circuit, particularly according to the multi-tanh principle, having a first input node and a second input node, a first differential amplifier coupled to the first and second input nodes, and having a first offset voltage, and a second differential amplifier coupled to the first and second input nodes, and having a second offset voltage different from the first offset voltage. A first resistance circuit is coupled between the first differential amplifier and at least one current source, and a second resistance circuit is coupled between the second differential amplifier and the at least one current source. Varying of the current sources enables control of the transconductance without degrading linearity.

Transconductor circuit

A frequency synthesizer circuit that reduces undesired spurious sidebands while maintaining phase noise performance having a phase locked loop circuit comprising at least a phase detector, a controlled oscillator, a frequency divider coupled to the controlled oscillator for adjusting a frequency division of the frequency divider in response to a received control signal generated from a divisor value, a dithering circuit for providing a dither signal, and a sigma-delta modulator comprising an input for receiving a multi-bit input signal indicative of at least part of the divisor value. The input of the sigma-delta modulator is coupled with the dithering circuit for receiving the dither signal as a most significant bit of the multi-bit input signal.

Frequency synthesizer circuit comprising a phase locked loop

A low noise, highly linear transconductor circuit, which may be applied, e.g., in communication systems, includes a first input node for receiving a first input signal of the transconductor circuit and a second input node for receiving a second input signal of the transconductor circuit, and at least a first amplifier, a second amplifier, and a first, second and third resistor. Each of the first and second amplifiers includes an input stage with a combination of at least a transistor of the MOS type and a transistor of the bipolar type, and an output stage for providing a respective output signal of the transconductor circuit and having at least a transistor of the bipolar type. The circuit achieves reduced noise due to output current reuse in the input stage of the amplifiers and cross coupling of bias resistors to result in a highly linear transconductor circuit having very low noise.

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Grassbrunn, Germany

Sebastian Zeller