Oracle International Corporation

Xilinx, Inc.

Oracle America, Inc.

Sun Microsystems, Inc.

Sebastian Turullols

Yifan YangGong

Changku Hwang

Ravinder Sharma

Ali Vahidsafa

Haowei Zhang

Venkatram Krishnaswamy

Vijay Srinivasan

Xiaoying Shen

Daniel S Woo

Aly E Orady

Lin Zhang

James Jiahua Yu

Georgios K Konstadinidis

Ha Pham

Jayaram Pvss

Ch Vamshi Krishna

Kaustuv Manji

Siva Santosh Kumar Pyla

Daisy Jian

Robert Paul Masleid

David James Riddoch

Steven Leslie Pope

Derek Edward Roberts

Robert T Golla

Sumti Jairath

Amit Kumar

Sonal Santan

Qing Xie

Thomas M Wicki

Kieran Mansley

David J Greenhill

Ramaswamy Sivaramakrishnan

Stephen P Rozum

Kyle Corbett

Mark Semmelmeyer

Ravi Nagarajarao Kurlagunda

Stephen Phillips

Sudipto Chakraborty

Cheng Zhen

Scott Cooke

Andrew C Yang

Deboleena Minz Sakalley

Brian F Keish

King Cheung Yen

Min Ma

Senthilkumar Diraviam

Manjunath Chepuri

Nicolas M Huynh

Susheel Kumar Puthana

Himanshu Choudhary

Preethi Sama

Pranjal Joshi

Raj Kumar Rampelli

Yufei Qian

Nilay Shah

Naga Murali Narasimha Rao Medeme

Kaustuvmani Manji

Indlamuri Hemanth Kumar

Yifan Yanggong

Ravi N Kurlagunda

Methods and systems to manage an environmental condition, such as power consumption and/or temperature, of an integrated circuit (IC) device by controlling a bandwidth of a packet-based communication interface of the IC device (e.g., a PCIe interface). Bandwidth may be controlled by controlling delay between packets or controlling delay of a handshake signal. Delay may be increased when the environmental condition reaches a first threshold. Delay may be reduced when the environmental condition falls to a second threshold. Bandwidth may be regulated with proportional-integral control provided by a firmware controller and/or hardware. Bandwidth may be separately controlled for upstream and downstream paths based on bandwidth utilization of the respective paths. Bandwidth control may utilize codes stored in selectable registers. The IC device may include a field programmable gate array (FPGA) and may be configured as an accelerator card.

Power and temperature driven bandwidth throttling using delay insertion

Embodiments herein describe a host that polls a network adapter to receive data from a network. That is, the host/CPU/application thread polls the network adapter (e.g., the network card, NIC, or SmartNIC) to determine whether a packet has been received. If so, the host informs the network adapter to store the packet (or a portion of the packet) in a CPU register. If the requested data has not yet been received by the network adapter from the network, the network adapter can delay the responding to the request to provide extra time for the adapter to receive the data from the network.

Host polling of a network adapter

A power management controller is disclosed. Broadly speaking, the controller may, in response to receiving a timing signal, monitor a temperature of an integrated circuit including multiple processor clusters. The controller may generate a comparison of the temperature and a threshold value, and in response to a determination that the comparison indicates that the temperature is less than the threshold value, transition a particular processor cluster to a new power state.

Temperature based frequency throttling

A method for determining power dissipation within a computer system is disclosed. A circuit block may receive a regulated voltage level on a power supply signal generated by a voltage regulator circuit. A power control circuit may measure a current drawn by the circuit block, and determine a real-time voltage level for the power supply signal using the current and based on a slope value and a zero-load voltage level. Additionally, power control circuit may determine a power dissipation for the circuit block using the current and the real-time voltage level, and adjust an operation parameter of the circuit block based on the power dissipation.

Load line compensation in power monitoring

Using a flat shell for an accelerator card includes reading a flat shell from one or more computer readable storage media using computer hardware, wherein the flat shell is a synthesized, unplaced, and unrouted top-level circuit design specifying platform circuitry. A kernel specifying user circuitry is synthesized using the computer hardware. The kernel is obtained from the one or more computer readable storage media. The synthesized kernel is linked, using the computer hardware, to the flat shell forming a unified circuit design. The unified circuit design is placed and routed, using the computer hardware, to generate a placed and routed circuit design specifying the platform circuitry and the user circuitry for implementation in an integrated circuit.

Flat shell for an accelerator card

Embodiments herein describe techniques for managing power consumption and temperature in an electronic circuits or integrated chips driven by clock signals (collectively referred to as 'cards') by throttling the clock signals on those cards. The cards often allow users to implement customized hardware acceleration functions via Field Programmable Gate Arrays or the like, which can lead to variable workloads on different cards (or regions of individual cards) based on the customized functionality. By throttling the clock signal based on continuously monitored power consumption or temperature, the user is enabled to use the card more aggressively (e.g., based on average rather than worst-case power consumption), and the card automatically throttles operations when power consumption or temperature exceeds operational thresholds.

Power and temperature driven clock throttling

A system is disclosed, including an interface to a DUT and a testing apparatus. The DUT includes a first plurality of temperature sensing circuits. The testing apparatus may store a plurality of control values. Each control value may depend on at least two calibration values of corresponding temperature sensing circuits of a second plurality of temperature sensing circuits. The testing apparatus may generate a plurality of calibration values for the DUT. Each calibration value corresponds to one of the first plurality of temperature sensing circuits. The testing apparatus may determine a plurality of test values for the DUT. The testing apparatus may calculate a probability value, and repeat generation of the plurality of calibration values upon determining that the probability value is less than a predetermined threshold value. The probability value corresponds to a likelihood that the plurality of calibration values is accurate.

Adaptive method for calibrating multiple temperature sensors on a single semiconductor die

A hardware acceleration device can include a switch communicatively linked to a host central processing unit (CPU), an adapter coupled to the switch via a control bus, wherein the control bus is configured to convey addresses of descriptors from the host central CPU to the adapter, and a random-access memory (RAM) coupled to the switch through a data bus. The RAM is configured to store descriptors received from the host CPU via the data bus. The hardware acceleration device can include a compute unit coupled to the adapter and configured to perform operations specified by the descriptors. The adapter may be configured to retrieve the descriptors from the RAM via the data bus, provide arguments from the descriptors to the compute unit, and provide control signals to the compute unit to initiate the operations using the arguments.

High throughput circuit architecture for hardware acceleration

A method for adjusting operation parameters of a computer system based on power consumption of the computer system is disclosed. During a power state transition of the computer system, a voltage level of a power supply signal may be sampled at a plurality of time points to generate a multiple voltage level samples. A voltage level of a selected one of the multiple voltage level samples may be adjusted using a particular coefficient of multiple coefficients to generate an updated voltage level sample. A power consumption of the computer system may be determined using the updated voltage level sample, and based on the power consumption, at least one operation parameter of the computer system may be adjusted.

Current compensation during dynamic voltage and frequency scaling transitions

A method and apparatus for calibrating a temperature sensor is disclosed. In one embodiment, a method comprises generating first and second digital values based respectively on first and second voltages applied to a portion of a temperature sensor circuit. An arithmetic circuit may derive the value of the second voltage based on the first and second digital values. The method further comprises determining an initial value of a constant based on values of the first and second voltages, and determining a final value of the constant based on the initial voltage and at least one voltage offset. The constant may then be used in determining temperature readings for the temperature sensor.

Statistical temperature sensor calibration apparatus and methodology

Embodiments include systems and methods for in-system, scan-based device testing using novel narrow-parallel (NarPar) implementations. Embodiments include a virtual automated test environment (VATE) system that can be disposed within the operating environment of an integrated circuit for which scan-based testing is desired (e.g., a chip under test, or CuT). For example, the VATE system is coupled with a service processor and with the CuT via a novel NarPar interface. A sequence controller can drive a narrow set of parallel scan pins on the CuT via the NarPar interface of the VATE system in accordance with an adapted test sequence having bit vector stimulants and expected responses. Responses of the CuT to the bit vector stimulants can be read out and compared to the expected results for scan-based testing of the chip.

Narrow-parallel scan-based device testing

A power management controller is disclosed. Broadly speaking, the controller may, in response to detecting a timing signal, determine a total power consumption for a plurality of processor clusters, each of which includes a plurality of processor cores. The controller may determine a performance metric using the total power consumption and compare the performance metric to a limit. Based on a result of the comparison, the controller may select a new power state for at least one of the processor clusters.

Power management in an integrated circuit

Growing community of inventors

Los Altos, CA, United States of America

Sebastian Turullols