International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries U.S. Inc.

Marvell Asia Pte., Ltd.

Other

Sebastian Theodore Ventrone

Kenneth Joseph Goodnow

Clarence Rosser Ogilvie

Joseph Andrew Iadanza

Alvar Antonio Dean

Anthony Richard Bonaccio

Jack Robert Smith

Hayden C Cranford, Jr

Keith Robert Williams

Igor Arsovski

Kerry Bernstein

John Maxwell Cohn

Vibhor Jain

Wilbur David Pricer

Christopher B Reynolds

Richard Stephen Graf

Pradeep Thiagarajan

Yves T Ngu

Jason Michael Norman

Pascal A Nsame

David James Hathaway

Patrick Edward Perry

John J Ellis-Monaghan

Charles S Woodruff

Scott Alan Tetreault

William R Tonti

Michel S Michail

Serafino Bueti

Ezra D B Hall

Scott Whitney Gould

Nancy H Pratt

Hemen R Shah

Siva P Adusumilli

Susan K Lichtensteiger

Todd Edwin Leonard

Johnatan A Kantarovsky

Faraydon Pakbaz

Michael Richard Ouellette

Douglas Willard Stout

Sudeep Mandal

Anthony J Perri

Jack Allan Mandelman

Claude Louis Bertin

Wagdi William Abadeer

Paul Steven Zuchowski

Stephen Dale Wyatt

Ivan L Wemple

Francis A Kampf

Jagannathan Narasimhan

Emory D Keller

Mariette Awad

Jeffrey P Gambino

Gordon Taylor Davis

David E Lackey

David W Milton

Sunil Kumar Singh

Charles Joseph Masenas

John J Reilly

Paul Mark Schanely

John E Campbell

Raminderpal Singh

Casey Jon Grant

Theodoros Anemikos

William T Devine

Stephen William Mahin

Jesse Ethan Craig

Peter Joel Jenkins

Baozhen Li

Rohit Pradeep Shetty

Baiju Dhirajlal Mandalia

Robert Mark Rassel

Rajarao Jammy

Fen Chen

George Maria Braceras

Wen Liu

Nazmul Habib

Michael Anthony Sorna

Steven Frederick Oakland

Eric D Hunt-Schroeder

Janak G Patel

Jerry D Hayes

Anthony M Palagonia

Anthony D Polson

Robert Maurice Houle

Mete Erturk

Robert Spencer Horton

Keishi Okamoto

Kevin A Batson

Garrett Stephen Koch

Benjamin T Voegeli

Mark Steven Styduhar

Shawn A Adderly

Bret Roberts Dale

Roger Paul Gregor

Keith A Ford

Elie Awad

Alfred Degbotse

Jason Edward Rotella

Richard James Evans

Adam J Courchesne

Structures with an isolation region and fabrication methods for a structure having an isolation region. The structure includes a semiconductor substrate, a first isolation region surrounding a portion of the semiconductor substrate, a device in the portion of the semiconductor substrate, and a second isolation region surrounding the first isolation region and the portion of the semiconductor substrate.

Isolation regions for charge collection and removal

The disclosure provides an integrated circuit (IC) structure with fluorescent materials, and related methods. An IC structure according to the disclosure may include a layer of fluorescent material on an IC component. The layer of fluorescent material defines a portion of an identification marker for the IC structure.

Integrated circuit structure with fluorescent material, and related methods

The present disclosure relates to integrated circuits, and more particularly, to an anti-tamper x-ray blocking package for secure integrated circuits and methods of manufacture and operation. In particular, the present disclosure relates to a structure including: one or more devices on a front side of a semiconductor material; a plurality of patterned metal layers under the one or more devices, located and structured to protect the one or more devices from an active intrusion; an insulator layer between the plurality of patterned metal layers; and at least one contact providing an electrical connection through the semiconductor material to a front side of the plurality of metals.

Anti-tamper x-ray blocking package

The disclosure provides a method to authenticate an integrated circuit (IC) structure. The method may include forming a first authentication film (AF) material within the IC structure. A composition of the first AF material is different from an adjacent material within the IC structure. The method includes converting the first AF material into a void within the IC structure. Additionally, the method includes creating an authentication map of the IC structure to include a location of the void in the IC structure for authentication of the IC structure.

Method and related structure to authenticate integrated circuit with authentication film

An integrated circuit (IC) includes functional logic therein that can be enabled by application of a predefined thermal cycle. The IC includes an enabling fuse operatively coupled to the functional logic, the functional logic being disabled unless enabled by activation of the enabling fuse. A set of thermal sensors are arranged in a physically distributed manner through at least a portion of the IC. A test control macro operatively couples to the set of thermal sensors and the enabling fuse for activating the enabling fuse to enable the functional logic in response to application of a thermal cycle that causes the set of thermal sensors to sequentially experience a thermal condition matching a thermal sequence enabling test. A related method and system for applying the predefined thermal cycle are also provided.

Enabling of functional logic in IC using thermal sequence enabling test

The present disclosure relates to an active x-ray attack prevention structure for secure integrated circuits. In particular, the present disclosure relates to a structure including a functional circuit, and at least one latchup sensitive diode circuit configured to induce a latchup condition in the functional circuit, placed in proximity of the functional circuit.

Active attack prevention for secure integrated circuits using latchup sensitive diode circuit

The present disclosure relates to a metal layer for an active x-ray attack prevention device for securing integrated circuits. In particular, the present disclosure relates to a structure including a semiconductor material, one or more devices on a front side of the semiconductor material, a backside patterned metal layer under the one or more devices, located and structured to protect the one or more devices from an active intrusion, and at least one contact providing an electrical connection through the semiconductor material to a front side of the backside patterned metal layer. The backside patterned metal layer is between a wafer and one of the semiconductor material and an insulator layer.

Active x-ray attack prevention device

The present disclosure relates to a structure including a first delay path circuit which is configured to receive an input signal and is connected to a complement transistor of a twin cell transistor pair through a complement bitline signal, a second delay path circuit which is configured to receive the input signal and is connected to a true transistor of the twin cell transistor pair through a true bitline signal, and a logic circuit which is configured to receive a first output of the first delay path circuit and a second output of the second delay path circuit and output a data output signal.

Sensing circuits for charge trap transistors

Embodiments of the disclosure provide systems and methods to operate a logic circuit with non-deterministic clock edge variations. A system may include a clock coupled to a logic circuit, the logic circuit having a set of source latches coupled to a set of capture latches through a set of logic cones. The clock includes a fixed clock component configured to generate a clock signal having a first clock edge, and a jitter clock component coupled to the fixed clock component and configured to modify the clock signal to have a second clock edge based on a non-deterministic value. The clock transmits the clock signal with the second clock edge to drive the set of source latches and the set of capture latches of the logic circuit. A clock controller coupled to the jitter clock component generates the non-deterministic value.

System and method to drive logic circuit with non-deterministic clock edge variation

Embodiments of the disclosure provide a low power multiplexer (MUX) circuit, including: a first data input coupled to an input of a first pass gate device; a second data input coupled to an input of a second pass gate device; a hold latch having an input coupled to a data output of the MUX circuit and an output coupled to an input of a supplemental pass gate device; and a pulse generator for generating a HOLD pulse signal, wherein the HOLD pulse signal is coupled to a control input of the supplemental pass gate device. The hold latch is configured to hold a previously valid output data signal of the MUX circuit until a valid input data signal is available at the first data input or the second data input.

Transition once multiplexer circuit

Aspects of the present disclosure provide an integrated circuit (IC) wafer having a plurality of circuit dies each bounded by a set of scribe lines. The IC structure includes: a plurality of reference features each respectively positioned in a first layer of one of the plurality of circuit dies. The reference feature of each circuit die is equidistant from a respective set of scribe lines for the circuit die, and a plurality of identification features each positioned in a second layer of one of the plurality of circuit dies. The reference feature of each circuit die has a distinct offset vector indicative of a positional difference between the identification feature for the circuit die and the reference feature for the circuit die, relative to the identification feature of each other circuit die.

IC wafer for identification of circuit dies after dicing

Chip packages with improved tamper resistance and methods of using such chip packages to provide improved tamper resistance. A lead frame includes a die attach paddle, a plurality of outer lead fingers, and a plurality of inner lead fingers located between the outer lead fingers and the die attach paddle. A chip is attached to the die attach paddle. The chip includes a surface having an outer boundary and a plurality of bond pads arranged proximate to the outer boundary. A first plurality of wires extend from the outer lead fingers to respective locations on the surface of the chip that are interior of the outer boundary relative to the bond pads. A tamper detection circuit is coupled with the first plurality of wires. A second plurality of wires extend from the inner lead fingers to the bond pads on the chip. The second plurality of wires are located between the lead frame and the first plurality of wires.

Tamper detection for a chip package

Structures for integrated lasers, systems including integrated lasers, and associated fabrication methods. A ring waveguide and a seed region are arranged interior of the ring waveguide. A laser strip extends across a portion of the ring waveguide. The laser strip has an end contacting the seed region and another opposing end. The laser strip includes a laser medium and a p-n junction capable of generating electromagnetic radiation. The p-n junction of the laser strip is aligned with a portion of the ring waveguide.

III-V lasers with on-chip integration

The present disclosure generally relates to semiconductor structures and, more particularly, to stacked dies using one or more interposers and methods of manufacture. The structure includes: at least one die comprising a plurality of via interconnects, the plurality of via interconnects comprising at least one functional via interconnect, one defective via interconnect and one redundant functional via interconnect to compensate for the one defective via interconnect; and an interposer which includes interconnects that aligns to and electrically connects the at least one functional via interconnect and the redundant functional via interconnect of different dies when the interposer is oriented in a predetermined orientation.

Stacked dies using one or more interposers

The present disclosure relates to semiconductor structures and, more particularly, to optical via connections in chip-to-chip transmission in a 3D chip stack structure using an optical via, and methods of manufacture. The structure has a first wafer, including a first waveguide coupled to an optical resonator in the first wafer, and a second wafer, including a second waveguide, located over the first wafer. The structure also includes an optical via extending between the optical resonator of the first wafer and the second waveguide of the second wafer to optically couple the first and second waveguides.

Optical through silicon via

Growing community of inventors

South Burlington, VT, United States of America

Sebastian Theodore Ventrone