Infineon Technologies Ag

Sebastian Sattler

Heinz Mattes

Hans-Dieter Oberle

Stephane Kirmser

Claus Dworski

Michael Goessel

Andreas Leininger

Thomas Piorek

Olaf Stroeble

An evaluation circuit and method for detecting faulty data words in a data stream is disclosed. In one embodiment the evaluation circuit according to the invention includes a first linear automaton circuit and also a second linear automaton circuit connected in parallel, each having a set of states z, which have a common input line for receiving a data stream T. The first linear automaton circuit and the second linear automaton circuit are designed such that a first signature and a second signature, respectively, can be calculated. Situated downstream of the two linear automaton circuits are respectively a first logic combination gate and a second logic combination gate, which compare the signature respectively calculated by the linear automaton circuit with a predeterminable good signature and output a comparison value.

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M periods of the test signal and of the reference signal are received. The periods of the test signal and of the reference signal are in each case Tlong. The test signal is sampled with N sampled values at a sampling frequency f=1/T. Also, N*T=M*T, where N&#x3e;M. The sampled values are numbered progressively by n, for which 0&#x2266;n &#x2266;N&#x2212;1. The sampled values have a defined relative phase shift with respect to the reference signal. The phase shift Tis calculated by K being a constant and Idx(i) corresponding to the number n which is either the first sampled value after a test signal zero crossing during the reference signal's iperiod or the last sampled value before a test signal zero crossing during the reference signal's iperiod. Either only rising or only falling zero crossings are taken into account.

Measuring device and method for measuring relative phase shifts of digital signals

An electrical test circuit is disclosed. In one embodiment, the electrical test circuit includes a first input for receiving a test signal of an integrated circuit, a second input for receiving a control signal and a third input for receiving a normalized reference signal, particularly one that is formed to be synchronous with the test signal. Using a control device of the electrical test circuit, the deviation and/or the amplitude and/or the phase of the reference signal and/or of the test signal can be varied. A measuring device generates, by subtracting the reference signal from the test signal, a difference signal which is output via an output.

Electrical circuit and method for testing electronic component

A test apparatus for testing digitized test responses has a generator and a signal extractor. The generator uses direct digital synthesis to generate a set of n digital reference signals which are orthogonal to one another. In this case, n is a natural number greater than 1. The signal extractor contains a test input and reference inputs. The test input receives a digitized test response and the reference inputs are connected to the reference signals which are generated by the generator. The signal extractor generates scalar products from a respective reference signal and the test response and uses the products to calculate whether a combination of reference signals is contained in the test response.

Test apparatus for digitized test responses, method for testing semiconductor devices and diagnosis method for a semiconductor device

An electrical circuit used for measuring times is disclosed. In one embodiment, the electrical circuit has a counter, a decoder and a multiplicity of time trap elements. At least the counter and the time trap elements are located together on an integrated semiconductor component. Each time trap element has a data input, a clock input, a delay output and a output port. The time trap element contains a delay element and a flip flop. The delay element outputs a signal change at the data input with a time delay at the delay output. The flip flop has a data input, a clock input and an output port, the data inputs, the clock inputs and the output ports of the flip flop and of the time trap element being connected to one another. The time trap elements are connected as ring oscillator.

Electrical circuit for measuring times and method for measuring times

A test device contains a data pattern generator for providing a delta-sigma-modulated data stream sampled with a sampling frequency fat its output. A phase modulator generates a test clock subjected to jitter and having the clock frequency fat its output. The output of the data pattern generator is connected to a terminal for connection to a data input of a semiconductor component to be tested. The output of the phase modulator is connected to a terminal for connection to a clock input of a semiconductor component to be tested. An evaluation device determines the jitter parameters of the input signal at the input of the data device from the low-frequency component of the input signal. In this case, the low-frequency component contains only frequency components of frequencies which are less than half the sampling frequency f/2.

Device and method for measuring jitter

An electric tolerance analysis circuit for digital and digitized measured values has inputs for receiving a measured value, a reference value, and a tolerance value and also an output for transmitting an output value. The electric tolerance analysis circuit also has a checking device for checking the measured value using at least one prescribable tolerance criterion and has an output device for outputting an output value which is obtained from the state of the checking device, depending on whether or not the measured value meets the respective prescribed tolerance criterion.

Apparatus and method for tolerance analysis for digital and/or digitized measure values

The electronic test circuit for an integrated circuit to be tested has an input for receiving an analog data stream (), a programmable digital line emulator (TPE) for emulating properties of a transmission path and an output for emitting an analog data stream () having a signal-to-noise ratio which can be adjusted using the programmable digital line emulator (TPE).

Electronic test circuit for an integrated circuit and methods for testing the driver strength and for testing the input sensitivity of a receiver of the integrated circuit

A test device and method is disclosed. In one embodiment, the test device includes a precision signal generator for generating a test signal, which generator is connected via a respective connecting line to a respective input contact intended for connection to an input of an integrated circuit, and at least one reference signal generator for generating a reference signal. Furthermore, at least one comparator unit is provided for a respective input contact said comparator unit being able to be operated in a test mode. In the test mode, the test signal is compared with the reference signal. The precision signal generator is turned off by the comparator unit if the test signal exceeds or falls below the reference signal.

Device and method for testing integrated circuits

A method for testing AD converters () may have the steps of a) producing a digital test signal, b) producing an analog test signal as input signal for the AD converter () from the digital test signal, c) producing a sinusoidal, digital reference signal whose frequency is equal to or an integer multiple of the frequency of the analog test signal, d) mixing the test response from the AD converter () with the sine and the cosine of the digital reference signal to form mixed signals, e) determining the DC components of the mixed signals, and f) determining at least one of the parameters including amplitude, power components and phase angle for a fundamental or harmonic of the test response from the DC components of the mixed signals.

Test apparatus and method for testing analog/digital converters

An electrical circuit including a test circuit and a method of testing electrical circuits is disclosed. In one embodiment, the circuit includes a electrical short-circuit protective circuit according to the invention for protecting an input contact against short-circuit having an input which is intended for connection to a signal generator, and an output which is intended for connection to a input contact. The input contact can be decoupled from the region lying upstream of the input of the electrical short-circuit protective circuit by the electrical short-circuit protective circuit.

Electrical circuit and method for testing integrated circuits

To determine the period length of a first signal, the length is measured by counting the periods of a second signal with a shorter period length. To measure the fluctuations of the period length of the first signal whilst also taking into account the fluctuations of the period length of the second signal, the measurement is carried out for two different values of the period length of the second signal. Both the fluctuations of the period length of the first signal and the accumulated fluctuations of the period length of the second signal are calculated independently of one another from the two values. The method enables the period length fluctuations of a first signal that originates from a phase-locked loop to be detected.

Method and device for detecting period length fluctuations of periodic signals

A semiconductor component is tested by providing a tester, a loadboard and an evaluation apparatus. The semiconductor component is operated using a test sequence, with the reference signal being applied to the semiconductor component or to the evaluation apparatus.

Test apparatus and test method for mixed-signal semiconductor components

In order to test the input and output drivers of a circuit, in particular an integrated semiconductor circuit, a method and apparatus is provided to connect the input or output drivers assigned to individual signal connections of the circuit to be tested in series to a ring oscillator or to an open chain with the oscillation of the ring oscillator or the delay time being evaluated. By providing appropriate controllable switches, the configuration of the ring oscillator or the chain can be altered variably depending on the input or output drivers to be tested respectively. In this way an 'at-speed' and 'leakage' test of all input and output drivers, including the external signal connections, are possible with all of these having to be connected to a rapid test unit.

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Munich, Germany

Sebastian Sattler