Infineon Technologies Ag

Sebastian Kuhne

Helmut Fischer

Bernd Klehn

Alexander Benedix

Thomas Janik

Helmut Schneider

Wolfgang Anton Spirkl

Georg Braun

Gunnar H Krause

Detlev Richter

Thoai-Thai Le

Roderick McConnell

A memory module is described which, externally, has the functionality of DDR SDRAMs and contains two groups of conventional SDRAMs. A conversion device provides for the conversion of clock signals, commands, and data. The conversion device contains a changeover switch, a delay locked loop and buffer memory for addresses and commands and also for the data, which are driven in a suitable manner by the delay locked loop.

DDR to SDR conversion that decodes read and write accesses and forwards delayed commands to first and second memory modules

A method and a configuration for the output of bit error tables from semiconductor devices are described. A test control unit reads the bit error table from the memory device following a request from the test apparatus. Then, the bit error tables are transmitted sequentially to the test apparatus for further processing.

Method and configuration for the output of bit error tables from semiconductor devices

A method and semiconductor circuit with which a self-test can be generated and tested with commands by which memory banks are interrogated simultaneously includes a processor for carrying out a built-in self-test and generating commands, each for testing only a respective single memory bank, and an additional processor connected downstream forms more complex multibank commands. Such multibank command formation enables a more diverse test of memories and is carried out faster. Principally, such multibank command generation using a combination of conventional single-bank commands has the advantage of not redeveloping a conventional BIST processor from scratch. It is necessary merely to connect a logic circuit downstream, with which conventional commands are combined, to form the multibank commands. As a result, complex self-test commands that simultaneously access a plurality of memory banks can be generated by a very low development outlay.

Test of a semiconductor memory having a plurality of memory banks

An integrated memory has a memory cell array, which is subdivided into a plurality of separate segments. A first and a second local word line in different segments together form a common global word line. The global word line is decoded via a row decoder. The first and second local word lines are connected to a column decoder in such a way that they can be decoded individually and segment by segment in a manner dependent on a column address. The memory thus allows fast and current-saving activation of a word line.

Integrated memory having a memory cell array with a plurality of segments and method for operating the integrated memory

A monolithically integrable inductor containing a layer sequence of conductive layers and insulating layers that are stacked mutually alternately above one another is described. The conductive layers are configured in such a way that they form a coil-type structure around a central region, in which giant magnetic resistance materials can be provided.

Monolithically integrable inductor

An integrated circuit has a differential amplifier in a basic circuit having two input transistors, a load element and a power source. The power source has an N-type channel MOS transistor whose controlled path is connected to the input transistors and to a supply terminal of the power source. A control terminal of the transistor is connected to a potential that is positive with respect to a reference potential. The supply terminal of the power source is connected to a potential which is negative with respect to the reference potential and which is made available by a voltage source for switching off cell field transistors of a DRAM memory. The gate-source voltage that is increased in this way improves the behavior of the circuit with respect to fluctuations in potential and permits more favorable dimensioning of the transistor.

Integrated circuit with a differential amplifier

A pulse generator circuit, in particular for use in or for integrated circuits, which, in the usual way, has a number of inverting elements connected in series, a logic combining element and a delay element. A buffer circuit provided in accordance with the invention ensures that a minimum pulse length of the output pulse generated in response to the input signal is ensured even in the case of an input signal of a very short duration.

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Radebeul, Germany

Sebastian Kuhne