Technische Universitát Dresden

Technische Universitaet Dresden

Siliconally Gmbh

Sebastian Hoeppner

Thomas Hocker

Markus Winter

Andreas Dixius

Felix Neumaerker

Stephan Hartmann

Stefan Haenzsche

Benedikt Schonlau

A method and timing recovery circuit for recovering a sampling clock from a serial data stream encoded using Pulse-Amplitude-Modulation applies a filter pattern decoder to detected symbol sequence at more than two adjacent data symbols, particularly to the detected symbol patterns of four adjacent samples ŷ(k−2), ŷ(k−1), ŷ(k), ŷ(k+1), and calculates an estimated phase error e(k).

Method and timing recovery circuit for recovering a sampling clock from a serial data stream encoded using PAM

A method for generating random numbers on multiprocessor systems and a multiprocessor system for generating true random numbers, using the method, generate truly random numbers with high entropy in a multiprocessor system with little additional effort to chip area and power dissipation. The method includes the steps of: measuring a phase error signal of a clock generator circuit of a first and a second processing unit respectively, forwarding the phase error signal of the respective clock generator circuit of the first and second processing unit to a true random network, combining the phase error signal of the clock generator circuit of the first processing unit and the phase error signal of the clock generator circuit of the second processing unit in the true random network to random bit streams, picking-up a random bit stream of the true random network, passing the respective random bit stream back to a random generator of the respective processing unit for outputting true random.

Method for generating true random numbers on a multiprocessor system and the same

A method and an arrangement for generating a clock signal by a phase locked loop in which the time for adjusting to a prescribed frequency and phase of a clock signal is reduced by virtue of the fact that a plurality of selection signals respectively shifted by a time difference delta t are generated from the divided clock signal. A comparison signal (capture) is generated under control by an edge of the reference clock and a comparison is started in the case of which what is selected is that selection signal shifted by delta t which exhibits with its edge the least possible time deviation from the edge of the comparison signal, and the selected selection signal is output.

Method and arrangement for generating a clock signal by means of a phase locked loop

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Dresden, Germany

Sebastian Hoeppner