International Business Machines Corporation

Sebastian Ehrenreich

Juergen Pille

Otto M Wagner

Juergen Koehl

Jente Benedict Kuang

Derick Gardner Behrends

Otto Andreas Torreiter

Tilman Gloekler

Chun-Tao Li

Hung Cai Ngo

Dieter F Wendel

Anthony Gus Aipperspach

Rolf Sautter

Markus Buehler

Willm Hinrichs

Jens Kuenzer

Werner Juchmes

Thomas Buechner

Torsten Mahnke

Hung Kai Ngo

Bruno U Spruth

Atnje Mueller

Silke Salewski

A signal repowering chip comprises an input; at least one inverter connected in series to the input; and at least one switch connected to a test enable signal, the at least one switch configured to allow a signal connected to the input to propagate through the at least one inverter in the event that the test enable signal is on. A 3-dimensional integrated circuit comprises a first chip, the first chip comprising a default voltage level and a plurality of wiring layers; and a second chip, the second chip comprising at least one repeater, the repeater being connected to the default voltage level.

Signal repowering chip for 3-dimensional integrated circuit

The invention relates to a voltage regulator circuit for providing voltage to an integrated circuit chip, comprising a reference voltage generator providing a reference voltage, a pFET header device having a plurality of pFET fingers, wherein each pFET finger in the plurality of pFET fingers is adapted for providing a different pFET output voltage to the integrated circuit chip, and a pFET control device for switching the plurality of pFET fingers depending on a comparison between the reference voltage and the pFET output voltage. The voltage regulator circuit allows for dynamically switching on or off the pFET fingers based on the output of the comparison of the reference voltage and the pFET output voltage, and thus allows for dynamically switching on or off, respectively, at least partly the integrated circuit chip.

On-die voltage regulation using p-FET header devices with a feedback control loop

An improved method monitors memory circuits, especially those used in integrated circuits. The method provides: writing random data in at least one monitor cell, which is implemented as a regular memory cell with an artificially deteriorated stability in order to provoke early fails when compared to fails in a regular memory cell; reading the random data out of the at least one monitor cell; comparing the output data of the read operation against an expected value to detect a value mismatch; and reporting the value mismatch to an error structure if the value mismatch is detected.

Method, system, computer program product, and data processing device for monitoring memory circuits and corresponding integrated circuit

The invention relates to a wordline booster circuit, especially an SRAM-wordline booster circuit, comprising a driving element () for shifting a voltage level of a charge storage element () for storing a charge necessary to generate a boosted voltage (Vb), a feedback element () for controlling the switching state of a charging element (), wherein the charging element () is actively switchable between a turned-off state during a first time interval and a turned-on state during a second time interval, and an output port () for supplying the boost voltage to at least one wordline-driver circuit () of a memory device (). The invention relates also to an operation method for such a wordline booster circuit as well as a memory array implementation on an integrated circuit, especially an SRAM memory array, with a wordline booster circuit.

Wordline booster design structure and method of operating a wordine booster circuit

A method to read and write at least one static memory cell is provided, said cell comprising a cross-coupled inverter pair and two pass-devices wherein said method is characterized in that during read only one of the two pass-devices is selected, while for write both pass-devices are selected. Furthermore, a circuit to read and write at least one static memory cell is described, said cell comprising a cross-coupled inverter pair and two pass-devices. Said circuit is characterized in that for each pass-device of the cell an individual wordline is connected with a gate of the particular pass-device, wherein both wordlines are selected for write and a single wordline is selected for read.

Single-ended read and differential write scheme

A structure and method to reduce leakage of a Static Random Access Memory (SRAM) array, wherein the array is subdivided into a set of sub-arrays, whose supply voltages can be controlled independently using a single voltage regulation circuit dedicated to the entire SRAM array. A switch fabric enables independent switching of individual sub-arrays between a virtual ground level and a system ground level based on whether the sub-array is operating in power saving mode or a high performance mode to reduce leakage current when a sub-array is configured in a power saving mode.

Method to reduce leakage of a SRAM-array

A signal distribution tree structure for distributing signals within a plurality of signal tree branches to a plurality of signal sinks, wherein the signal in subsequent sub trees () is driven by a preceding amplifier (), which is characterized in that the amplifiers are logic gates (), which combines the signals of a preferred input () connected to a preceding logic gate in the signal path with a signal of a secondary input () connected to an adjacent tree () path of a neighboring and/our preceding sub tree.

Redundancy in signal distribution trees

A design structure embodied in a machine readable medium to improve performance of an SRAM cell or an SRAM array comprising a plurality of SRAM cells is described. The design structure includes a write circuit for an SRAM cell or an SRAM array. The write circuit includes a gate to switch the write circuit on and off. The cell is supplied by a first, higher voltage. The cell is accessible for read and write operations via at least one bit line connected to a write circuit. The cell is further addressable by at least one word line in order to access it by the bit line. To access the cell for read or write operations, the word line is supplied by the first, higher voltage and the bit line is supplied by a second, lower voltage. During write operations, the write circuit is driven by the first, higher voltage while the bit lines are still at the lower voltage.

Design structure for improving performance of SRAM cells, SRAM cell, SRAM array, and write circuit

Wordline booster circuit and method of operating a wordline booster circuit

A method to improve performance of an SRAM cell or an SRAM array comprising a plurality of SRAM cells is described. The cell is supplied by a first, higher voltage. The cell is accessible for read and write operations via at least one bit line connected to a write circuit. The cell is further addressable by at least one word line in order to access it by the bit line. To access the cell for read or write operations, the word line is supplied by the first, higher voltage and the bit line is supplied by a second, lower voltage. During write operations, the write circuit is driven by the first, higher voltage while the bit lines are still at the lower voltage. An SRAM cell, an SRAM array plus a write circuit used to perform the method are also described.

Method to improve performance of SRAM cells, SRAM cell, SRAM array, and write circuit

A storage cell design evaluation circuit including a wordline timing and cell access detection circuit provides accurate information about state changes in static storage cells. A storage cell test row includes the access detection circuit, which provides the same loading during an access operation as the other cells in the array. The access detection circuit provides an output that may be probed without affecting the timing, read stability or writeability of the cell. The test row can test the clock and/or address timing of the row and may include a separate power supply rail for the row wordline driver, so that variation of access timing, read stability and writeability with wordline strength/access voltage can be determined. Multiple test rows may be cascaded among columns to provide a long delay line or ring oscillator for improved measurement resolution.

Storage cell design evaluation circuit including a wordline timing and cell access detection circuit

A method for bypassing a memory array in a circuit having a global bit line, a test port configured to output a logic test, a memory portion connected to the global bit line via a word line, a header device being connected to the global bit line via a pre-charge signal, the header device being configured to recharge the global bit line. A gating signal is sent to a gating device connected to the header device. The gating device is switched to a test mode upon receipt of the gating signal. The bypass data signal is sent to an evaluating device connected to the gating device, the evaluating device being configured to output a logic test. The logic test is output through the test port upon receipt of bypass data signal.

Bypass circuit for memory arrays

Asymmetrical random access memory cell () including cross coupled inverters () which are driven at their nodes () by separate bit-lines (blt, blc) of a pair of complementary bit-lines, which are connected via a pass-transistor (), wherein the random access memory cell is asymmetrical by means of the cross coupled inverters () which have asymmetrically physical behaviours whereby different switching thresholds of the inverters are present, and that the pass-transistors () are driven by separate controlled wordlines (wl, wwl).

Asymmetrical random access memory cell, and a memory comprising asymmetrical memory cells

A method for storage cell design evaluation provides accurate information about state changes in static storage cells. A wordline select pulse is propagated along the wordline select path of the test row to an output driver circuit, in order to test the clock and/or address timing of the row, so that variation of access timing, read stability and writeability with wordline strength/access voltage can be determined. An access detection cell holds the input of the output driver circuit until a simulated access operation activated by the wordline select pulse is complete. Multiple test rows may be cascaded among columns to provide a long delay line or ring oscillator for improved measurement resolution.

Method for evaluating storage cell design using a wordline timing and cell access detection circuit

A signal distribution tree structure for distributing signals within a plurality of signal tree branches to a plurality of signal sinks, wherein the signal in subsequent sub trees () is driven by a preceding amplifier (), which is characterized in that the amplifiers are logic gates (), which combines the signals of a preferred input () connected to a preceding logic gate in the signal path with a signal of a secondary input () connected to an adjacent tree () path of a neighboring and/or preceding sub tree.

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Schoenau, Germany

Sebastian Ehrenreich