Epcos Ag

Qualcomm Incorporated

Tdk Electronics Ag

Sebastian Brunner

Thomas Feichtinger

Christian Faistauer

Günter Pudmich

Stefan Leopold Hatzl

Klaus-Dieter Aichholzer

Edmund Payr

Gerhard Fuchs

Christian Block

Oliver Dernovsek

Kurt Wiesbauer

Patrick Schmidt-Winkel

Horst Schlick

Annette Fischer

Changhan Hobie Yun

Christian Hoffmann

Franz Rinner

Reinhard Gabl

Axel Pecina

Martin Galler

Robert Krumphals

Dieter Somitsch

Pavol Dudesek

Georg Krenn

Stefan Obermair

Manuel Hofer

Guenter Pudmich

Alois Kleewein

Franz Kaul

Horst Droescher

Florian Rak

Manfred Fischer

Yasuharu Miyauchi

Johann Ramler

Stephan Steinhauser

Stefan Leitinger

Franz Tinauer

Andreas Haas

Horst Uwe Faulhaber

A package comprising an acoustic device, a polymer frame coupled to the acoustic device, a plurality of frame interconnects located in the polymer frame, where the plurality of frame interconnects are coupled to the acoustic device, a polymer cap layer coupled to the acoustic device though the polymer frame, where the polymer cap layer is configured as a cap for the acoustic device, a plurality of cap interconnects located in the polymer cap layer, where the plurality of cap interconnects are coupled to the plurality of frame interconnects, and a cavity located between the acoustic device and the polymer cap layer. The acoustic device includes a substrate and an acoustic element coupled to the substrate.

Package comprising an acoustic device and a polymer cap layer

A package that includes an integrated device, a substrate coupled to the integrated device, and an encapsulation layer coupled to the substrate. The encapsulation layer encapsulates the integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects located in the at least one dielectric layer, wherein at least one of the interconnects has a rectangular side cross-section having at least one corner with a corner radius less than a corner radius threshold.

Package including a substrate with high resolution rectangular cross-section interconnects

A mechanically stable main body having a cutout, into which an ESD protection element is at least partly embedded and mechanically fixed by means of a connection means. Electrical terminals of the protection element are connected to terminal pads on the top side of the main body by way of a structured metallic layer bearing on main body and protection element.

Component substrate having a protective function

A package that includes an integrated device, a substrate coupled to the integrated device, and an encapsulation layer coupled to the substrate. The encapsulation layer encapsulates the integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects located in the at least one dielectric layer, a buffer dielectric layer coupled to the at least one dielectric layer, and a buffer interconnect located at least in the buffer dielectric layer.

Package comprising a substrate that includes a stress buffer layer

A multi-LED system is disclosed. In an embodiment a multi-LED system includes a ceramic multilayer substrate in which at least two ESD protection structures are integrated, at least two light-emitting diodes arranged on the substrate and at least two capping layers covering one of the light-emitting diodes.

Multi-LED system

A green film composed of varistor material laminated on a ceramic main body, which is provided with metallizations on both sides, and is sintered to form a varistor layer. A terminating electrode pair completes the arrangement and allows the varistor layer to be operated as a varistor. The upper second electrode pair can serve directly as a terminal contact for mounting an electrical component.

Component carrier having an ESD protective function and method for producing same

A component assembly is disclosed. In an embodiment the assembly includes a carrier, a metallic structure arranged on the carrier, wherein the metallic structure comprises at least one cavity and an electrical component arranged at least in part in the cavity, wherein the metallic structure comprises at least two part regions which are not connected to each other by any further part of the metallic structure, and wherein the cavity is located between the two part regions. The assembly further includes two contact areas located on the carrier, wherein the component is located on the two contact areas such that each part region of the two part regions is located on one of the two contact areas.

Electric component assembly

A carrier plate includes a substrate and at least one conductor track. The conductor track includes a first layer, which is applied directly on the substrate, and a second layer, which is arranged on the first layer. The second layer includes a supply line region and a soldering region. Furthermore, the second layer is completely interrupted between the supply line region and the soldering region. A device can be produced with a carrier plate and an electrical component arranged on the carrier plate.

Carrier plate, device having the carrier plate and method for producing a carrier plate

A method for producing an electric contact-connection of a multilayer component is disclosed. In an embodiment, the method includes providing a main body of the multilayer component having internal electrode layers, applying an electrically conductive material and applying a photosensitive material on the electrically conductive material. The method further includes structuring the electrically conductive material via the photosensitive material such that the internal electrode layers alternatingly are covered and uncovered by the electrically conductive material and applying an insulating material after structuring the electrically conductive material such that the internal electrode layers are alternatingly covered by the electrically conductive material and by the insulating material.

Method for producing an electric contact connection of a multilayer component

A chip and a method for manufacturing a chip are disclosed. In an embodiment, the chip includes a varistor layer composed of zinc oxide, a multilayered electrode structure which realizes a varistor function in the varistor layer and at least two solderable or bondable external contacts on a first main surface of the varistor layer. The chip further includes a glass layer disposed on the first main surface leaving only the external contacts uncovered, wherein the glass layer includes, as main constituents, oxides of Si and/or Ge, B and K, which in total have at least 70% by weight of the constituents of the glass layer, and wherein the glass layer is substantially free of Al, Ga, Cr and Ti.

Chip with protection function and method for producing same

A light-emitting diode device includes a carrier having at least one cavity, a light-emitting diode chip is arranged in a manner at least partly recessed in the at least one cavity, and an ESD protection element, which is formed by a partial region of the carrier. Furthermore, a light-emitting diode device includes a carrier having at least one cavity, a light-emitting diode chip arranged on the carrier, and an electrical component arranged at least partly recessed in the at least one cavity. Furthermore, the light-emitting diode device includes an ESD protection element, which is formed by a partial region of the carrier.

Light-emitting diode device

A light-emitting diode device has a first carrier and at least one light-emitting diode chip, which is arranged on the first carrier. The first carrier has at least one first and one second carrier part, wherein the light-emitting diode chip rests only on the first carrier part. Furthermore, the first and second carrier parts each have a thermal conductivity. The thermal conductivity of the first carrier part is at least 1.5 times the thermal conductivity of the second carrier part. The first carrier part is surrounded laterally by the second carrier part.

A light-emitting diode arrangement includes a light-emitting diode and a coding resistor for coding the light-emitting diode. The coding resistor is embodied as a star connection of a number of resistors. Furthermore, a module includes a plurality of light-emitting diode arrangements. Furthermore, a method for producing a light-emitting diode arrangement is specified, wherein the coding of a coding resistor is carried out depending on a determined characteristic of the light-emitting diode.

Light-emitting diode arrangement, module, and method for producing a light-emitting diode arrangement

A method for producing an electrical component, comprises providing a ceramic semiconducting base body () having a surface (O) and a first side area (S) lying opposite the surface (O), wherein a metallic layer () is contained within the base body. After at least two further metallic layers () have been arranged separately from one another on the side area (S) of the base body, the arrangement is sintered. An electrically insulating layer () is arranged between the at least two further metallic layers (). A respective contact layer () is arranged on the metallic layers () by means of a chemical process. In this case, the material of the base body () is removed proceeding from the surface (O) of the base body () at most as far as the metallic layer () arranged within the base body.

Method for producing an electrical component, and electrical component

A method for patterning a layer stack with at least one ceramic layer includes providing the ceramic layer, which has at least one plated-through hole. An electrically conductive layer is applied above the ceramic layer, such that the electrically conductive layer is electrically coupled to the at least one plated-through hole. A further layer is deposited onto the electrically conductive layer in the region of the at least one plated-through hole, wherein the further layer includes nickel. The electrically conductive layer is removed outside the region of the at least one plated-through hole. A carrier device patterned in this way can be electrically and mechanically coupled to an electronic component.

Growing community of inventors

Graz, Austria

Sebastian Brunner