Intel Corporation

Sean T Murphy

Orville H Christeson

Douglas L Gabel

James H Ewertz

Peter D MacWilliams

Narjala Prakash Bhasker

Douglas L Gabe

Stephen J Packer

A method and an apparatus for protection of a private directory such as those provided by AT&T.RTM.'s WorldWorx.SM. Personal Conferencing Service in a wide area network. A directory is protected through a requirement of a valid user identification number and matching password providing access rights to certain secured directory information residing in the wide area network.

Multi-privileged level directory access on the AT&T worldworxsm personal

A computer system wherein a portion of code/data stored in a non-volatile memory device can be dynamically modified or updated without removing any covers or parts from the computer system. The computer system of the preferred embodiment includes a flash memory component coupled to a computer system bus for storing non-volatile code and data. Using the present invention, the contents of a portion of the flash memory may be replaced, modified, updated, or reprogrammed without the need for removing and/or replacing any computer system hardware components. The flash memory device used in the preferred embodiment contains four separately erasable/programmable non-symmetrical blocks of memory. One of these four blocks may be electronically locked to prevent erasure or modification of its contents once it is installed. This configuration allows the processing logic of the computer system to update or modify any selected block of memory without affecting the contents of other blocks. One memory block contains a normal BIOS. An electronically protected flash memory area is used for storage of a recovery BIOS which is used for recovery operations. The present invention also includes hardware for selecting one of the two available update modes: normal or recovery. Thus, using a mode selection apparatus, either a normal system BIOS or a recovery BIOS may be activated.

Dynamic non-volatile memory update in a computer system

A computer system wherein a paging technique is used to expand the useable non-volatile memory capacity beyond a fixed address space limitation. The computer system of the preferred embodiment includes a flash memory component for storing non-volatile code and data including a system BIOS in the upper 128K of memory. The useful BIOS memory space is effectively increased while maintaining the address boundary of the upper 128K region. The address space of the non-volatile memory device is logically separated into distinct pages of memory (Pages 1-4). Using the apparatus and techniques of the present invention, Page 1, Page 3 and Page 4 may be individually swapped into the address space originally occupied by Page 1 (the swappable page area). In the preferred embodiment, Page 2 is held static and thus is not used as a swap area. Each of the swappable pages, Page 1, Page 3, and Page 4, contain processing logic called swapping logic used during the swapping or paging operation. The swapping logic operates in conjunction with paging hardware to effect the swapping of pages into the swappable page area. The high order processor address lines are input by a page decoder. The page decoder is used to modify the address actually presented to the non-volatile memory device. A page register provides a means by which the processor may select a page in non-volatile memory. In an alternative embodiment of the present invention, several different forms of configuration or identification information may be stored in a page of non-volatile memory.

Computer system with a paged non-volatile memory

A computer system wherein a paging technique is used to expand the usable non-volatile memory capacity beyond a fixed address space limitation. The computer system of the preferred embodiment includes a flash memory component for storing non-volatile code and data including a system BIOS in the upper 128K of memory. The useful BIOS memory space is effectively increased while maintaining the address boundary of the upper 128K region. The address space of the non-volatile memory device is logically separated into distinct pages of memory (Pages 1-4). Page 1, Page 3 and Page 4 may be individually swapped into the address space originally occupied by Page 1 (the swappable page area). In the preferred embodiment, Page 2 is held static and thus is not used as a swap area. Each of the swappable pages contain processing logic called swapping logic used during the swapping or paging operation. The swapping logic operates in conjunction with paging hardware to effect the swapping of pages into the swappable page area. The high order processor address lines are input by a page decoder. The page decoder is used to modify the address actually presented to the non-volatile memory device. A page register is used by the processor to select a page in non-volatile memory. In an alternative embodiment, several different forms of configuration or identification information may be stored in a page of non-volatile memory.

A high speed serial bus is disclosed have particular application for use in passing messages in a multiple processor computer system. The serial bus includes a three-wire serial link having lines identified as 'SDA', 'SDB' and 'ground'. The ground line provides a common reference for all devices coupled to the serial bus. A message controller is coupled to each agent for transmitting and receiving serial data along the bus. Both lines of the serial bus as well as the ground are coupled to a bus state detector in the message controller which provides three basic signal outputs. The bus state detector determines whether or not the bus is in use, a collision has occurred between messages, and decodes data received on the bus. Data which is transmitted along the serial bus is driven on lines SDA and SDB 180 degrees out of phase relative to each other. The message controller encodes messages to be transmitted using, in the present embodiment, well known Manchester encoding techniques. A bus idle state occurs when all transmitters are off allowing both lines SDA and SDB be pulled high by pull-up resistors. Valid data states may occur any time a single transmitter is transmitting. When two or more transmitters begin transmitting a collision state exists. The message controller recognizes collisions and provides a back-off algorithm.

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Portland, OR, United States of America

Sean T Murphy