Intel Corporation

Sean T Baartmans

Tsvika Kurts

Bryan R White

Todd M Witter

Jason Sandri

Marcelo Yuffe

Marcus R Winston

Arie Bernstein

Eilon Hazan

Michael J Wiznerowicz

Rony Ghattas

Ruben Ramirez

A processing device comprises a debug port controller to monitor operations of the processing device to determine whether the processing device is operating in a first mode or a second mode and to collect trace information comprising operating characteristics of the processing device. The processing device further comprises a display engine logic to process display data for output to a display device. In addition, the processing device comprises a display engine interface to provide, to a plurality of existing platform connectors, the display data from the display engine logic when the processing device is operating in the first primary mode and the trace information from the debug port controller when the processing device is operating in the second mode as determined by the debug port controller.

High-speed debug port using standard platform connectivity

In one embodiment, the present invention is directed to a logic analyzer such as may be implemented on a system-on-chip or another semiconductor device. The analyzer can include multiple lanes each having a filter to receive and filter debug data, a compressor to compress the debug data passed by the filter, a buffer, and a controller to store the compressed debug data into the buffer, where the compressed debug data can be stored without timing information. Other embodiments are described and claimed.

Providing an on-die logic analyzer (ODLA) having reduced communications

In one embodiment, the invention may include a logic structure integrated in an integrated circuit (IC), that has a set of bus inputs to generate events, a mask register to select inputs from among the set of bus inputs, a logic register to select logic to apply to the selected inputs and an event output to supply the result of the applied logic. The embodiment may further include a bus interface integrated in the IC and coupled to the logic structure to transmit settable parameters to the mask register and the logic register of the logic structure from an external agent.

Customizable event creation logic for hardware monitoring

Growing community of inventors

Portland, OR, United States of America

Sean T Baartmans