Intel Corporation

Sean O Stalley

David J Harriman

Debendra Das Sharma

Rajesh M Sankaran

Stephen R Van Doren

Rupin H Vakharwala

Pratik M Marolia

Daniel S Froelich

Mahesh U Wagh

Akshay G Pethe

Manjari Kulkarni

Systems and devices can include a controller and a command queue to buffer incoming write requests into the device. The controller can receive, from a client across a link, a non-posted write request (e.g., a deferred memory write (DMWr) request) in a transaction layer packet (TLP) to the command queue; determine that the command queue can accept the DMWr request; identify, from the TLP, a successful completion (SC) message that indicates that the DMWr request was accepted into the command queue; and transmit, to the client across the link, the SC message that indicates that the DMWr request was accepted into the command queue. The controller can receive a second DMWr request in a second TLP; determine that the command queue is full; and transmit a memory request retry status (MRS) message to be transmitted to the client in response to the command queue being full.

Non-posted write transactions for a computer bus

Aspects of the embodiments are directed to systems, methods, and computer program products that facilitate a downstream port to operate in Separate Reference Clocks with Independent Spread Spectrum Clocking (SSC) (SRIS) mode. The system can determine that the downstream port supports one or more SRIS selection mechanisms; determine a system clock configuration from the downstream port to a corresponding upstream port connected to the downstream port by the PCIe-compliant link; set an SRIS mode in the downstream port; and transmit data across the link from the downstream port using the determined system clock configuration.

System, method, and apparatus for SRIS mode selection for PCIE

System, method, and apparatus for SRIS mode selection for PCIe

Packets may be compressed based on predictive analyses. For example, in one embodiment, it is determined that an explicit value for a particular header field can be inferred by the receiver agent, a packet header is constructed that either omits the header field or includes a differential value for the header field in lieu of the explicit value for the header field. The packet header may be decompressed upon receipt by deriving the explicit value for the particular header field.

Predictive packet header compression

An interconnect switch is provided including switching logic executable to facilitate a Peripheral Component Interconnect Express (PCIe)-based interconnect, and further including a control host embedded in the switch to provide one or more enhanced routing capabilities. The control host includes a processor device, memory, and software executable by the processor device to process traffic received at one or more ports of the switch to redirect at least a portion of the traffic to provide the one or more enhanced routing capabilities.

Architecture for software defined interconnect switch

Described is an apparatus which comprises: a transmitter; an input-output (I/O) interface coupled to the transmitter; and logic to split data for transmission into a plurality of packets, wherein each packet is stored in a buffer and then transmitted via the I/O interface to a receiver, wherein the logic can vary a number of packets sent prior to the transmitter receiving an Acknowledgement (ACK) signal, and wherein the logic can vary a packet length of the number of packets.

Growing community of inventors

Hillsboro, OR, United States of America

Sean O Stalley