Intel Corporation

Sean Mirkes

Srinivas Chennupaty

Mark P Seconi

Michael A Julier

Jeffrey D Gray

Martin Guy Dixon

Vinodh Gopal

Bret L Toll

Maxim Loktyukhin

Gilbert M Wolrich

Wajdi K Feghali

James D Guilford

Erdinc Ozturk

Mark C Davis

Alexandre J Farcy

Elmoustapha Ould-Ahmed-Vall

Eric W Mahurin

David L Kreitzer

Matthew C Merten

Tong Li

Srikanth T Srinivasan

Robert S Chappell

James Hadley

Ammon J Christiansen

Erdine Ozturk

Thomas Mullins

James D Gulilford

Waidi K Feghali

Vindoh Gopal

Maxim Loktyukin

Bret T Toll, I

A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.

Rotate instructions that complete execution either without writing or reading flags

Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.

Instruction and logic for processing text strings

A number of addition instructions are provided that have no data dependency between each other. A first addition instruction stores its carry output in a first flag of a flags register without modifying a second flag in the flags register. A second addition instruction stores its carry output in the second flag of the flags register without modifying the first flag in the flags register.

Addition instructions with independent carry chains

In one embodiment, a reservation station of a processor includes: a plurality of first lanes having a plurality of entries to store information for instructions having in-order dependencies; a variable latency tracking table including a second plurality of entries to store information for instructions having a variable latency; and a scheduler circuit to access a head entry of the plurality of first lanes to schedule, for execution on at least one execution unit, at least one instruction from the head entry of at least one of the plurality of first lanes. Other embodiments are described and claimed.

System, apparatus and method for a hybrid reservation station for a processor

Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value to a bit of the source operand in a corresponding position; and (2) second range of bits that all have a same value regardless of values of bits of the source operand in corresponding positions. Execution of instruction may complete without moving the first range of the result relative to the bits of identical value in the corresponding positions of the source operand, regardless of the location of the first range of bits in the result. Execution units to execute such instructions, computer systems having processors to execute such instructions, and machine-readable medium storing such an instruction are also disclosed.

Processor to perform a bit range isolation instruction

A method in one aspect may include receiving a multiply instruction. The multiply instruction may indicate a first source operand and a second source operand. A product of the first and second source operands may be stored in one or more destination operands indicated by the multiply instruction. Execution of the multiply instruction may complete without writing a carry flag. Other methods are also disclosed, as are apparatus, systems, and instructions on machine-readable medium.

Multiplication instruction for which execution completes without writing a carry flag

System-on-chip (SoC) to perform a bit range isolation instruction

Hand held device to perform a bit range isolation instruction

Growing community of inventors

Beaverton, OR, United States of America

Sean Mirkes