International Business Machines Corporation

Globalfoundries Inc.

Sean M Polvino

Unoh Kwon

Shahab Siddiqui

Takashi Ando

Vijay Narayanan

Ravikumar Ramachandran

Aritra Dasgupta

Wing L Lai

Shahrukh Akbar Khan

Joseph Francis Shepard, Jr

Yue Ke

Kriteshwar Kaur Kohli

Benjamin G Moser

Mohammad Hasanuzzaman

A semiconductor device or article includes a substrate including a feature and divided into a feature region in which the feature is formed and a pad region in which the substrate is substantially unmodified, and a layer of interest applied over the substrate and feature. The pad and feature regions are irradiated and resulting photoelectron intensities are recorded and used to determine a thickness of the layer of interest over the feature. In addition, if the layer of interest includes an atomic species distinct from any in the substrate, an actual dose of the atomic species can be determined.

Non-destructive dielectric layer thickness and dopant measuring method

One aspect of the disclosure relates to and integrated circuit structure and methods of forming the same. The integrated circuit structure may include: a thin gate dielectric device on a substrate, the thin gate dielectric device including: a first interfacial layer over a set of fins within the substrate, wherein the interfacial layer has a thickness of approximately 1.0 nanometers (nm) to approximately 1.2 nm; and a thick gate dielectric device on the substrate adjacent to the thin gate dielectric device, the thick gate dielectric device including: a second interfacial layer over the set of fins within the substrate; and a nitrided oxide layer over the second interfacial layer, wherein the nitrided oxide layer includes a thickness of approximately 3.5 nm to approximately 5.0 nm.

Integrated circuit structure having thin gate dielectric device and thick gate dielectric device

Methods of forming a semiconductor fin and methods for controlling dopant diffusion to a semiconductor fin are disclosed herein. The methods provide alternative ways to incorporate a carbon dopant into the fin to later control out-diffusion of dopants from a dopant-including epitaxial layer. One method includes depositing a carbon-containing layer over a portion of the fin adjacent to the gate and annealing to diffuse carbon from the carbon-containing layer into at least the portion of the semiconductor fin. This method can be applied to SOI or bulk semiconductor substrates. Another method includes epitaxially growing a carbon dopant containing semiconductor layer for later use in forming the fin.

Methods of forming semiconductor fin with carbon dopant for diffusion control

After removal of the disposable gate structures to form gate cavities in a planarization dielectric layer, a silicon oxide layer is conformally deposited on silicon-oxide-based gate dielectric portions in the gate cavities. A portion of the silicon oxide layer can be nitridated to form a silicon oxynitride layer. A patterned masking material layer can be employed to physically expose a semiconductor surface from a first-type gate cavity. The silicon oxide layer can be removed while preserving an underlying silicon-oxide-based gate dielectric portion in a second-type gate cavity. A stack of a silicon oxynitride layer and an underlying silicon-oxide-based gate dielectric can be protected by a patterned masking material layer in a third-type gate cavity during removal of the silicon oxide layer in the second-type gate cavity. A high dielectric constant gate dielectric layer can be formed in the gate cavities to provide gate dielectrics of different types.

Multiple thickness gate dielectrics for replacement gate field effect transistors

A method of deep trench isolation which includes: forming a semiconductor on insulator (SOI) substrate comprising a bulk semiconductor substrate, a buried insulator layer and a semiconductor layer on the buried insulator layer (SOI layer), one portion of the SOI substrate having a dynamic random access memory buried in the bulk semiconductor substrate (eDRAM) and a deep trench fin contacting the eDRAM and a second portion of the SOI substrate having an SOI fin in contact with the buried insulator layer; conformally depositing sequential layers of oxide, high-k dielectric material and sacrificial oxide on the deep trench fin and the SOI fin; stripping the sacrificial oxide over the SOI fin to expose the high-k dielectric material over the SOI fin; stripping the exposed high-k dielectric material over the SOI fin to expose the oxide layer over the SOI fin.

High-K dielectric structure for deep trench isolation

Embodiments relate to a field-effect transistor (FET) replacement gate apparatus. The apparatus includes a channel structure including a base and side walls defining a trench. A high-dielectric constant (high-k) layer is formed on the base and side walls of the trench. The high-k layer has an upper surface conforming to a shape of the trench. A first layer is formed on the high-k layer and conforms to the shape of the trench. The first layer includes an aluminum-free metal nitride. A second layer is formed on the first layer and conforms to the shape of the trench. The second layer includes aluminum and at least one other metal. A third layer is formed on the second layer and conforms to the shape of the trench. The third layer includes aluminum-free metal nitride.

Multi-layer work function metal replacement gate

Embodiments relate to a field-effect transistor (FET) replacement gate apparatus. The apparatus includes one or more of a substrate and insulator including a base and side walls defining a trench. A high-dielectric constant (high-k) layer is formed on the base and side walls of the trench. The high-k layer has an upper surface conforming to a shape of the trench. A first layer is formed on the high-k layer and conforms to the shape of the trench. The first layer includes an aluminum-free metal nitride. A second layer is formed on the first layer and conforms to the shape of the trench. The second layer includes aluminum and at least one other metal. A third layer is formed on the second layer and conforms to the shape of the trench. The third layer includes aluminum-free metal nitride.

Growing community of inventors

Brooklyn, NY, United States of America

Sean M Polvino