International Business Machines Corporation

Sean Hart

Patryk Gumann

Salvatore Bernardo Olivadese

Nicholas Torleiv Bronn

Daniela Florentina Bogorin

Devendra K Sadana

Stephen W Bedell

Ning Li

Steven J Holmes

Jay Michael Gambetta

Jerry M Chow

Layne A Berge

Trevor Joseph Timpane

Michael Scott Good

Curtis Eugene Larsen

Valerio A Grendanin

David Zarsky

Gilbert Bauer

Jason Scott Orcutt

Markus Brink

Sarunya Bangsaruntip

David C Mckay

Andrew W Cross

Oblesh Jinka

April Carniol

Raymond A Watters

Techniques facilitating custom thermal shields for cryogenic environments are provided. In one example, a cryostat can comprise a thermal shield extending between a thermal stage and a base structure coupled to a bottom plate of an outer vacuum chamber. The thermal stage can be coupled to a top plate of the outer vacuum chamber. The thermal shield can provide access to a sample mounting surface encompassed within the thermal shield from a region external to the outer vacuum chamber via the top and bottom plates of the outer vacuum chamber.

Custom thermal shields for cryogenic environments

A thermalization structure is formed using a cover configured with a set of pillars, the cover being a part of a cryogenic enclosure of a low temperature device (LTD). A chip including the LTD is configured with a set of cavities, a cavity in the set of cavities having a cavity profile. A pillar from the set of pillars and corresponding to the cavity has a pillar profile such that the pillar profile causes the pillar to couple with the cavity of the cavity profile within a gap tolerance to thermally couple the chip to the cover for heat dissipation in a cryogenic operation of the chip.

Cryogenic packaging for thermalization of low temperature devices

A quantum mechanical circuit includes a substrate; a first electrical conductor and a second electrical conductor provided on the substrate and spaced apart to provide a gap therebetween; and a third electrical conductor to electrically connect the first electrical conductor and the second electrical conductor. The third electrical conductor is a poor thermal conductor.

Ground discontinuities for thermal isolation

A gated Josephson junction includes a substrate and a vertical Josephson junction formed on the substrate and extending substantially normal the substrate. The vertical Josephson junction includes a first superconducting layer, a semiconducting layer, and a second superconducting layer. The first superconducting layer, the semiconducting layer, and the second superconducting layer form a stack that is substantially perpendicular to the substrate. The gated Josephson junction includes a gate dielectric layer in contact with the first superconducting layer, the semiconducting layer, and the second superconducting layer at opposing side surfaces of the vertical Josephson junction, and a gate electrically conducting layer in contact with the gate dielectric layer. The gate electrically conducting layer is separated from the vertical Josephson junction by the gate dielectric layer. In operation, a voltage applied to the gate electrically conducting layer modulates a current through the semiconducting layer of the vertical Josephson junction.

Superconductor-semiconductor Josephson junction

A quantum computing system includes a dilution refrigerator having a plurality of chambers. A trapped ion computing device includes a first set of qubits in a given chamber of the plurality of chambers of the dilution refrigerator. A superconducting computing device having a second set of superconducting qubits is inside the given chamber of the plurality of chambers of the dilution refrigerator.

Trapped ion architecture in a dilution refrigerator for use with superconducting qubit systems

Devices, systems, methods, computer-implemented methods, apparatus, and/or computer program products that can facilitate a suspendeddevice comprising an ion implant defined nanorod in a semiconducting device are provided. According to an embodiment, a quantum computing device can comprise adevice coupled to an ion implanted region. The quantum computing device can further comprise an encapsulation film coupled to the ion implanted region and a substrate layer. The encapsulation film suspends thedevice in the quantum computing device.

Ion implant defined nanorod in a suspended Majorana fermion device

Techniques facilitating increased operational reliability for jib cranes are provided. In one example, a jib crane can comprise a mast, a shaft mechanism, and a rod. The mast can extend vertically from a base structure. The shaft mechanism can be disposed within the mast. The rod can be coupled to a boom arm and can be disposed within the shaft mechanism. Rotation of the rod can facilitate continuous rotation of the boom arm about a longitudinal axis of the rod with respect to the base structure.

Jib crane mechanism

A quantum computer includes a refrigeration system under vacuum including a containment vessel, a qubit chip contained within a refrigerated vacuum environment defined by the containment vessel. The quantum computer further includes a plurality of interior electromagnetic waveguides and a plurality of exterior electromagnetic waveguides. The quantum computer further includes a hermetic connector assembly operatively connecting the interior electromagnetic waveguides to the exterior electromagnetic waveguides while maintaining the refrigerated vacuum environment. The hermetic connector assembly includes an exterior multi-waveguide connector, an interior multi-waveguide connector, and a dielectric plate arranged between and hermetically sealed with the exterior multi-waveguide connector and the interior multi-waveguide connector. The dielectric plate permits electromagnetic energy when carried by the interior and exterior pluralities of electromagnetic waveguides to pass therethrough.

High density microwave hermetic interconnects for quantum applications

Techniques for designing and fabricating quantum circuitry, including a coplanar waveguide (CPW), for quantum applications are presented. With regard to a CPW, a central conductor and two return conductor lines can be formed on a dielectric substrate, with one return conductor line on each side of the central conductor and separated from it by a space. The central conductor can have bridge portions that can be raised a desired distance above the substrate and base conductor portions situated between the bridge portions and in contact with the surface of the substrate; and/or portions of the substrate underneath the bridge portions of the central conductor can be removed such that the bridge portions, whether raised or unraised, can be the desired distance above the surface of the remaining substrate, and the base conductor portions can be in contact with other portions of the surface of the substrate that were not removed.

Low loss conductive line using bridged conductor

Techniques regarding determining the temperature of one or more quantum computing devices are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a temperature component that can determine a temperature of a superconducting resonator based on a frequency shift exhibited by the superconducting resonator due to a change in kinetic inductance with a change in temperature.

On-chip thermometer for superconducting quantum computing devices

A system for transmission of quantum information for quantum error correction includes an ancilla qubit chip including a plurality of ancilla qubits, and a data qubit chip spaced apart from the ancilla qubit chip, the data qubit chip including a plurality of data qubits. The system includes an interposer coupled to the ancilla qubit chip and the data qubit chip, the interposer including a dielectric material and a plurality of superconducting structures formed in the dielectric material. The superconducting structures enable transmission of quantum information between the plurality of data qubits on the data qubit chip and the plurality of ancilla qubits on the ancilla qubit chip via virtual photons for quantum error correction.

Superconducting interposer for the transmission of quantum information for quantum error correction

A quantum circuit includes a first qubit and a second qubit. A bus resonator transmission line is coupled between the first qubit and the second qubit. A readout bus is coupled to the first qubit. A switch is coupled to the bus resonator transmission line between the first qubit and the second qubit.

DC conversion of half- to quarter-wave resonators for crosstalk suppression in superconducting qubits

A superconducting coupling device includes a resonator structure. The resonator structure has a first end configured to be coupled to a first device and a second end configured to be coupled to a second device. A gate is positioned proximal to a portion of the resonator structure. The gate is configured to receive a gate voltage and vary a kinetic inductance of the portion of the resonator based upon the gate voltage. The varying of the kinetic inductance induces the resonator structure to vary a strength of coupling between the first superconducting device and the second superconducting device.

Tunable superconducting resonator for quantum computing devices

A superconducting coupling device includes a resonator structure. The resonator structure has a first end configured to be coupled to a first device and a second end configured to be coupled to a second device. The device further includes an electron system coupled to the resonator structure, and a gate positioned proximal to a portion of the electron system. The electron system and the gate are configured to interrupt the resonator structure at one or more predetermined locations forming a switch. The gate is configured to receive a gate voltage and vary an inductance of the electron system based upon the gate voltage. The varying of the inductance induces the resonator structure to vary a strength of coupling between the first device and the second device.

Gate voltage-tunable electron system integrated with superconducting resonator for quantum computing device

Techniques regarding determining and/or analyzing temperature distributions experienced by quantum computer devices during operation are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a region component that can define a plurality of temperature regions from a quantum computing device layout. The computer executable component can also comprise a map component that can generate a map that characterizes a temperature distribution by determining at least one temperature achieved within the plurality of temperature regions during an operation of the quantum computing device layout.

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Sean Hart