Cypress Semiconductor Corporation

Sean Foley

Paul H Scott

Mohamed Sardi

Tony Blake

Bertrand Jeffery Williams

Carel Lombaard

Cazel Lombaard

A method and system for cycle slip framing is disclosed. The method includes receiving an asynchronous signal and generating a synchronous pulse after receiving the asynchronous signal. The method further provides that the synchronous pulse be used to affect a bit slip that results in the moving of a character frame in the recovered data of a deserializer. According to one embodiment of the invention, the moving of the character frame is prompted by a single control signal of a clock divider circuit which causes the removal of a single clock cycle of a clock signal supplied to said deserializer.

Method and system of cycle slip framing in a deserializer

A system and method are provided for synchronizing a frame of related bits output from a deserializer to the related bits serially fed to the deserializer. Synchronization is achieved by overcoming a slip bit problem by selectively increasing the frame clock cycle during times in which the slip bit occurs. The deserializer is controlled by a clock generator that can include a counter which generates the frame clock. The counter can be asynchronously or synchronously reset, without any glitches occurring within the deserializer and, thus, avoiding any invalid bits output from the deserializer. The asynchronous reset forces the counter to a deterministic state, and the synchronous reset sets the counter to a valid state. In each instance, however, resets do not impart glitches to the deserializer and the deserializer output frame is maintained synchronous to related bits serially fed to the deserializer.

Cycle slip framing system and method for selectively increasing a frame clock cycle to maintain related bits within the same parallel-output frame of a deserializer

A deserializer within, for example, a transceiver is provided having multiple stages of pipelined demultiplexers. Each demultiplexer within the earlier stages of the pipelined architecture use only three latches. Two latches are dedicated to producing an odd bitstream (or even bitstream) from odd and even bits within the incoming serial bitstream. Another latch is dedicated to producing an even bitstream (or odd bitstream) from even and odd bits of the serial bitstream. Using only three latches within early stages of the pipelined architecture reduces power consumption and overall size of the deserializer. Clocking signal frequencies of subsequent stages are reduced and the clocking signals are delayed in order to align data outputs from the previous stage with transitions of clocking signals forwarded to the respective stages.

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Cork, Ireland

Sean Foley