International Business Machines Corporation

Sean Dalton

Diyanesh B Chinnakkonda Vidyapoornachary

Tony Emile Sawan

Daniel Lewis

A circuit-cycle fault reproduction system includes a hardware processor configured to execute at least one computing cycle corresponding to a given number instructions. A cycle tracking unit is configured to identify at least one test cycle included in a range of computing cycles starting from at a start cycle and completing at an end cycle. A fail cycle detection unit is in signal communication with the cycle tracking unit. The fail cycle detection unit is configured to identify a failed cycle among the plurality of test cycles based on a cycle difference between the starting cycle and the ending cycle, and to actively modify the range of computing cycles based on a comparison between the cycle difference and a cycle difference threshold value.

Circuit-cycle reproduction

Critical path failure analysis using hardware instruction injection may include providing, by an instruction microcontroller, to a plurality of processor cores, one or more test instruction sequences, wherein the instruction microcontroller is coupled to, for each of the plurality of processor cores: a first multiplexor providing an input to an instruction queue, and a second multiplexer receiving an input from the instruction queue and providing an output to an execution pathway; performing, by the instruction microcontroller, based on one or more test instruction sequences, one or more of a scan-in last pass (SLP) analysis or a scan-in cycle offset (SCO) analysis; and determining, based on one or more of the SLP analysis or the SCO analysis, one or more of a critical instruction sequence or a critical component path associated with the plurality of processor cores.

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Austin, TX, United States of America

Sean Dalton