Texas Instruments Corporation

Sean Christopher O'Brien

Douglas A Prinslow

Guohong Zhang

John Charles Ehmke

Scott William Jessen

Lawrence D Dyer

Lucius Marshall Sherwin

Timothy J Hogan

Ronald Charles Roth

Jose Antonio Martinez

Scott Patrick Overmann

James T Manos

Mike Brenner

Lisa A Lester

In described examples, an image-generating panel is arranged for modulating a projection beam to include a modulated optical image. A cooling device is arranged to transfer heat received from the image-generating panel to a heat sink. The cooling device is arranged to receive the projection beam on a first side and to transmit the projection beam from a second side. The heat received from the image-generating panel can include heat generated by the image-generating panel in response to incidental sunlight.

Transparent display panel cooling

A microelectromechanical system (MEMS) is comprised of a micromirror device attached to a semiconductor device. A first spacer layer is formed and patterned to form hinge via openings. A hinge metal is deposited above the first spacer layer to form the hinge and the hinge vias. A capping layer is formed above the hinge metal and hinge vias. A second spacer layer is formed above the capping layer and patterned to form a mirror via. The capping layer protects the hinge metal from the developer solution used in the patterning step. The capping layer is removed from within the mirror via opening. Another metal layer is deposited above the second spacer layer to form the mirror and the mirror via.

Method of fabricating a MEMS device

A microelectromechanical (MEMS) device has a movable member supported above a substrate on a via support. The member and via support are fabricated integrally from first and second member forming layers. A first member forming layer forms a lower part of the member and supporting structure for the via support. First and second fill layers are deposited and patterned to form a plug that fills an inner cavity opening in the via structure. The plug is planarized to a planar part of the first member forming layer, and a second member forming layer is deposited over the first member forming layer and the planarized plug to form an upper part of the member. The via support may have a cavity filled by BARC layers.

MEMS device with improved via support planarization

Merging sub-resolution assist features includes receiving a mask pattern that includes the sub-resolution assist features. A first sub-resolution assist feature is selected to merge with a second sub-resolution assist feature. A merge bar width of a merge bar is established. A distance between the first sub-resolution assist feature and the second sub-resolution assist feature is determined. A merging technique is determined in accordance with the distance and the merge bar width. The first sub-resolution assist feature and the second sub-resolution assist feature are merged according to the identified merging technique.

Merging sub-resolution assist features of a photolithographic mask

In accordance with the invention, there is provided a system and method for checking a mask layout including sub-resolution assist features (SRAFs). A checking program divides each edge of each main feature into sections, forms a set of segments by searching perpendicularly over a distance to determine if any portion of a feature is located within the distance. Segments are then flagged based on whether a feature located within proximity to that segment. A classification program may then classify each of the main features based on the segment data.

System and method for checking for sub-resolution assist features

A method is provided for determining pitch of lithographic features of a mask. The method includes determining a bias based on an interaction between a plurality of reference features positioned according to a lithographic parameter of the mask, applying the bias to a plurality of lithographic features of the mask, and determining pitch of the plurality of lithographic features based on interactions between the biased plurality of lithographic features of the mask.

Methods and system for determining pitch of lithographic features

A design application improves design checking by utilizing a template. During the checking process, the design application divides the design layout into regions. To further improve processing speed, the design application utilizes the template. The template maps the location of the regions of a design layout during a checking process. The template comprises information such as the dimensions and location of the regions in human-readable form. Because the human-readable template is computationally simple to process, the design application may locate, divide, manage, and merge the regions of the design layout more quickly.

Methods and systems for performing design checking using a template

Modifying merged sub-resolution assist features includes receiving a mask pattern comprising the merged sub-resolution assist features, where a segmenting sub-resolution assist feature intersects a segmented sub-resolution assist feature at an intersection. Each sub-resolution assist feature is represented by an axis of the sub-resolution assist feature. The length of at least one axis is established, and an axis is modified in accordance with the length. Each axis is converted to a sub-resolution assist feature to yield the modified merged sub-resolution assist features.

Modifying merged sub-resolution assist features of a photolithographic mask

Merging sub-resolution assist features of a photolithographic mask through the use of a merge bar

Modifying sub-resolution assist features includes receiving a mask pattern for a photolithographic mask. The mask pattern includes main features, and the photolithographic mask is operable to pattern a wafer pattern for a semiconductor wafer. Placement of sub-resolution assist features for the main features is estimated. The following is repeated for one or more iterations: correcting the main features using a wafer pattern model operable to estimate the wafer pattern; evaluating the sub-resolution assist features according to the wafer pattern model; and modifying at least one sub-resolution assist feature in accordance with the evaluation.

Modifying sub-resolution assist features according to rule-based and model-based techniques

A self-aligned silicide process with a selective etch of unreacted metal (plus any nitride) with respect to silicide plus a two step process of highly selective strip of unreacted metal (plus any nitride) followed by a silicide etch to remove unwanted silicide filament.

Self-aligned silicide process

Self-aligned silicidation (e.g., Ti, Co, or Ni silicides) for silicon integrated circuits with an HF-based final etch of the silicide to remove filaments. Either ultradilute HF solution or HF vapor may be used.

Method of fabricating self-aligned silicide

A strip for TiN with selectivity to TiSi,consisting of a water solution of H,O,with possible small amounts of NH,OH.

Selective titanium nitride strip

A self-aligned silicide method with Ti deposition, reaction, strip of TiN with selectivity to TiSi.sub.2 consisting of a water solution of H.sub.2 O.sub.2 with possible small amounts of NH.sub.4 OH, phase conversion anneal, and then strip of TiSi.sub.2 filaments with a water solution of H.sub.2 O.sub.2 plus NH.sub.4 OH.

Growing community of inventors

Dallas, TX, United States of America

Sean Christopher O'Brien