3com Corporation

Sean Boylan

Tadhg Creedon

Kevin Jennings

Vincent Gavin

Denise De Paor

Kevin J Hyland

Suzanne M Hughes

Mike Lardner

Brendan Walsh

Derek Coburn

A program tool automatically generating interconnect logic for a system-on-a-chip is based on a library of operational cores and on a architecture which requires all data exchange between cores to proceed via shared memory, which may be 'off-chip'. The architecture includes a data aggregation technique for access to memory with successive levels of arbitration.

Automatic generation of interconnect logic components

An architecture for a system on a chip wherein functional cores have wrappers for compatibility with a common bus system and the bus system includes aggregators for bus transactions of different speeds and/or bus widths.

Asic system architecture including data aggregation technique

Growing community of inventors

Rahoon, Ireland

Sean Boylan