Cadence Design Systems, Inc.

Sean Bergan

Randall Scott Lawson

Ken Wadland

Richard Woodward

Patrick Bernard

Richard Allen Woodward, Jr

Jelena Radumilo-Franklin

Frank X Farmar

Charles Winston Grant

Paul S Musto

George Malcolm Buzzell

Brett Allen Neal

William Schilp

Joseph Dexter Smedley

Glendine Kingsbury

Steve Russo

Davis Tsai

Keith Woodward

Jia Wu

Keith Woodword

Gregory M Horlick

Kota Sujan Reddy

Walter M Katz

Greg Horlick

Donald Keith Morgan

Joe Smedley

Jelena Radumilo-Frankilin

The present disclosure relates to a method for multi-user, at least partially concurrent, electronic circuit design. Embodiments may include storing a lock list at a client computing device, wherein the lock list includes objects associated with an electronic design that have been locked or unlocked. Embodiments may further include receiving a user input corresponding to a lock/unlock request associated with an object of the design, wherein the design is accessible by multiple users in an at least partially concurrent manner. Embodiments may include transmitting the lock/unlock request to a server computing device. Embodiments may further include comparing the user input corresponding to at least one of the lock request or unlock request with the lock list and determining whether to lock or unlock the object based upon, at least in part, the comparison, wherein determining does not include receiving server authorization.

Concurrent design process

The present disclosure relates to a system and method for multi-user, at least partially concurrent, electronic circuit design. Embodiments may include displaying, at a first client computing device associated with a first user, at least a portion of an electronic circuit design, wherein the electronic circuit design is accessible by multiple users in an at least partially concurrent manner. Embodiments may further include processing a command at the first client computing device from the first user and receiving a temporary update from a server computing device, wherein the temporary update corresponds to a second user associated with a second client computing device. Embodiments may also include displaying, at the first client computing device, an operation corresponding to the received temporary update.

The present disclosure relates to a method for multi-user, at least partially concurrent, electronic circuit design. Embodiments may include receiving, at a client computing device, a user input corresponding to a change to an electronic circuit design, wherein the electronic circuit design is accessible by multiple users in an at least partially concurrent manner. Embodiments may also include implementing the change to the electronic circuit design at the client computing device without receiving authorization from a server computing device and transmitting the implemented change to the electronic circuit design to the server computing device.

The present disclosure relates to a system and method for multi-user, at least partially concurrent, electronic circuit design. Embodiments may include recording, at a client computing device, a plurality of operations associated with an electronic circuit design, wherein the electronic circuit design is accessible by multiple users in an at least partially concurrent manner. Embodiments may also include generating a script based upon, at least in part, the recorded operations and displaying, at the client computing device, at least a portion of the generated script.

A method, computer program product and apparatus for utilizing simulated locking prior to starting concurrent execution are disclosed. The results of this simulated locking are used to define a canonical ordering which controls the order of execution and the degree of parallelism that can be used.

Deterministic, parallel execution with overlapping regions

A system and method are provided for establishing an automated routing environment in an electronic design automation (EDA) work flow for the routing of a circuit design. A user may merely specify a flow via pattern, a flow via location, and a start and end terminal and thereby, the auto router or path finder will automatically find the least-cost paths between each of the start terminals through at least one intermediate via of the flow via and ending at an end terminal. Upon successful routing of all needed terminals, an at least partially routed circuit design may be output.

Method and system for routing optimally between terminals through intermediate vias in a circuit design

In one embodiment of the invention, an object oriented autorouter is disclosed for routing nets in a circuit. The object oriented autorouter includes a routing data model (RDM); at least one routing engine, such as a single connection router (SCR), a topographical (TOPO) transformation engine, and a detail geometric (DETAIL) engine, and a command and control module (CCM) coupled together. The RDM reads and write data with a design database as well as reading one or more object oriented design constraints. Each of the routing engines have at least one action to operate on the design database to improve compliance of the circuit to a constraint. The CCM controls the overall routing process of the nets in the circuit and includes at least one director to invoke at least one of the routing engines to achieve compliance with one or more constraints.

Systems for automatic circuit routing with object oriented constraints

Local constraints on placement of routing objects for direct connections between terminals in a circuit layout are determined from global constraints on the placement of the routing objects in a process referred to as global constraint budgeting. An autorouter finds paths in the layout to satisfy the local constraints and ignores the global constraints. The local constraints are updated before each routing pass to ensure that routes are completed on individual direct connections while also satisfying the global constraint.

Budgeting global constraints on local constraints in an autorouter

Circuit autorouter with object oriented constraints

A mechanism is provided for the user to define a circuit design intent or strategy in the form of data that is stored with the design database. An autorouter then uses this guidance from the user to create a plan for routing the design. The user can then modify their guidance to the router until the results for the plan are acceptable. Using the planned flow, the autorouter can complete the design, creating detailed paths including etch segments and vias. Allowing such interaction with an autorouter significantly reduces the routing time and hence time-to-market.

Growing community of inventors

Andover, MA, United States of America

Sean Bergan