Nvidia Corporation

Sean Benton Franey

Ross Segelken

Yusuf Cagatay Tekmen

Nickolas Andrew Fortino

Polychronis Xekalakis

Michael P Cornaby

Nikhita Kunati

Samuel Charles Tsen, Jr

David Hass

A first thread is executed in a first pipeline of a first core of an integrated circuit (IC). The first core includes a first set of hardware structures. A second thread is executed in a second pipeline of a second core of the IC. The second core includes a second set of hardware structures. In response to a command to operate the IC with a unified core, the first core is combined with the second core to obtain the unified core. To unify the first core, the first pipeline is unified with the second pipeline to obtain a unified pipeline, and the first set of hardware structures is unified with the second set of hardware structures to obtain a unified set of hardware structures. A single thread is executed in the unified pipeline of the unified core using the unified set of hardware structures.

Dynamic reconfiguration of a multi-core processor to a unified core

Growing community of inventors

Portland, OR, United States of America

Sean Benton Franey