Analog Devices Global

Analog Devices,inc.

Analog Devices International Unlimited Company

Seamus Paul Whiston

Edward John Coyne

William Allan Lane

Michael John Flynn

Patrick Martin McGuinness

Paul Martin Lambkin

Donal McAuliffe

Lynn Khine

Kotlanka Rama Krishna

Dennis A Dempsey

Bernard Patrick Stenson

David J Clarke

Jan Kubik

Andrew David Bain

Paul Malachy Daly

Brian Anthony Moane

Stephen Denis Heffernan

Michael Noel Morrissey

John Twomey

Denis J Doyle

Christina B McLoughlin

Brian Sweeney

David J Rohan

Andrew Christopher Linehan

Thomas J Lawlor

Mike O'Shea

Jagar Singh

Donai P McAuliffe

Padraig Michael Doran

The present disclosure relates to a field effect transistor (FET) structure. The FET structure has a substrate, an active region, a dielectric layer provided over a channel of the active region and a gate provided over the dielectric layer. The active region comprises a source, a drain and the channel provided between the source and the drain. The active region is surrounded by an isolation trench, such that width edges of the channel are directly adjacent to the isolation trench. Current paths run between the source and the drain, through the channel. The FET is configured such that current paths running proximal to the channel edges are reduced or weaker in comparison to a dominant current path running through a center of the channel. One or more of the channel, the dielectric layer or the substrate can be modified or adapted to provide the reduced and dominant current paths. In one example, the center of the channel away from the edges has a first doping concentration of a first conductivity type, and the sides of the channel along the channel edges have a second doping concentration of the first conductivity type, where the second doping concentration is greater than the first doping concentration. In another example, the dielectric layer is thicker over the sides of the channel and thinner over the center of the channel. In another example, regions of the substrate below the sides of the channel have a higher doping concentration than a region of the substrate below the center of the channel. In some examples, the FET structure has both the dielectric layer of different thicknesses and the different doping concentrations in the channel and/or the substrate.

Hybrid field-effect transistor

A microelectromechanical system (MEMS) device is provided that includes a substrate having a dielectric cavity formed therein and a movable electromechanical device suspended in the dielectric cavity. The dielectric cavity includes a substantially planar bottom surface and at least one sidewall surface extending substantially perpendicularly from the bottom surface. The movable electromechanical device is suspended in the dielectric cavity such that the movable electromechanical device is spaced apart from the bottom surface and the at least one sidewall surface of the dielectric cavity. The bottom surface of the cavity and each of the at least one sidewall surface of the cavity meet at a rectilinear corner.

Suspended microelectromechanical system (MEMS) devices

Suspended microelectromechanical systems (MEMS) devices including a stack of one or more materials over a cavity in a substrate are described. The suspended MEMS device may be formed by forming the stack, which may include one or more electrode layers and an active layer, over the substrate and removing part of the substrate underneath the stack to form the cavity. The resulting suspended MEMS device may include one or more channels that extend from a surface of the device to the cavity and the one or more channels have sidewalls with a spacer material. The cavity may have rounded corners and may extend beyond the one or more channels to form one or more undercut regions. The manner of fabrication may allow for forming the stack layers with a high degree of planarity.

Planar processing of suspended microelectromechanical systems (MEMS) devices

A modified bipolar transistor is provided which can provide improved gain, Early voltage, breakdown voltage and linearity over a finite range of collector voltages. It is known that the gain of a transistor can change with collector voltage. This document teaches a way of reducing this variation by providing structures for the depletion regions with the device to preferentially deplete with. As a result the transistor's response can be made more linear.

Bipolar transistor

Thin film resistive sensors typically include a number of resistive components. These components should be well matched in order for the sensor to provide accurate readings. When a sensor is incorporated within an integrated circuit, the resistive components may be formed over, or under, metallic traces that form part of other components. As a result, the thin film resistive components are subjected to different levels of stress. This disclosure provides a structure that is arranged to mitigate the effects of stress.

Thin film resistive device for use in an integrated circuit, an integrated circuit including a thin film resistive device

A method of trimming a component is provided in which the component is protected from oxidation or changes in stress after trimming. As part of the method, a protective glass cover is bonded to the surface of a semiconductor substrate prior to trimming (e.g., laser trimming) of a component. This can protect the component from oxidation after trimming, which may change its value or a parameter of the component. It can also protect the component from changes in stress acting on it or on the die adjacent it during packaging, which may also change a value or parameter of the component.

Method of trimming a component and a component trimmed by such a method

A protection device is provided that exhibits a turn on time of order of one nanosecond or less. Such a device provides enhanced protection for integrated circuits against electrostatic discharge events. This in turn reduces the risk of device failure in use. The protection device can include a bipolar transistor structure connected between a node to be protected and a discharge path.

Overvoltage protection device and method

A transistor is provided in which an elongate drain region has end portions formed in parts of the transistor where features of the transistor structure have been modified or omitted. These structures lessen the current flow or electric field gradients at the end portions of the drain. This provides a transistor that has improved on-state breakdown performance without sacrificing off state breakdown performance.

Transistor

A semiconductor device having a first layer adjoining a semiconductor layer, and further comprising at least one field modification structure positioned such that, in use, a potential at the field modification structure causes an E-field vector at a region of an interface between the semiconductor and the first layer to be modified.

Semiconductor device, and a method of improving breakdown voltage of a semiconductor device

Transistors having improved breakdown voltages and methods of forming the same are provided herein. In one embodiment, a method of forming a transistor comprises the steps of: forming a drain and a source by doping a semiconductor with a first dopant type to form a first type of semiconductor, the drain and source being separated from one another, wherein the drain comprises a first drain region of a first dopant concentration adjacent a second drain region, such that at least a portion of the second drain region is positioned between the first drain region and the source, and further comprising forming an intermediate region by doping the semiconductor so as to form a second type of semiconductor intermediate the drain and source, the intermediate region spaced apart from the second drain region.

Field effect transistors having improved breakdown voltages and methods of forming the same

A method for erasing an EEPROM cell which reduces the need for monitoring algorithms. The potential at the erase gate is initially raised and the potential at the control gate is lowered to cause FN tunneling through the erase gate. A subsequent soft programming step is employed to raise the potential at the control gate to a value sufficient to cause FN tunneling to start though the oxide of the transistor. A new memory device structure suitable for practicing this method employs a transistor having a floating gate, where a data value is stored as charged on the floating gate; a control gate; a control gate capacitor coupling the control gate to the floating gate; an erase gate; an erase gate capacitor coupling the erase gate to the floating gate; and an erase control circuit.

Method of erasing an EEPROM device

A method for forming an LDNMOS ( ) and LDPMOS ( ) in a CMOS process comprises forming the LDNMOS ( ) and LDPMOS ( ) to a stage where a gate ( ) is laid down on a gate oxide layer ( ) and a locos ( ) is formed over the respective N and P-wells ( ) and ( ) of the LDNMOS ( ) and LDPMOS ( ). A P-body ( ) is formed in the N-well ( ) of the LDNMOS ( ) by implanting a boron dopant in two stages, in the first stage at a first tilt angle (&thgr;) of 45&deg; for forming the P-body ( ) beneath the gate ( ) for determining the source/drain threshold voltage, and subsequently at a second tilt angle (&phgr;) of 7&deg; for extending the P-body ( ) downwardly at ( ) for determining the punchthrough breakdown voltage of the LDNMOS ( ). The formation of an N-body ( ) in a P-well ( ) of the LDPMOS ( ) is similar to the formation of the P-body ( ) with the exception that the dopant is a phosphorous dopant.

Growing community of inventors

Raheen, Ireland

Seamus Paul Whiston