Advanced Micro Devices Corporation

Microsoft Technology Licensing, LLC

Globalfoundries Inc.

Microsoft Technology Holding, LLC

Seah Sun Too

Raj N Master

Janet Kirkland

Mohammad A Khan

Maxat Touzelbaev

Jacquana T Diep

Paul Bornemann

Michael Joseph Lane

Tek Seng Tan

James L Hayward

Edward S Alcid

Kevin W Lim

Hsiang Wan Liau

Keng Sang Cha

Kee Hean Keok

Mohammad Zubair Khan

Leang Hua Kam

Ahmad Juwanda

Soon Tatt Ow Yong

Azlina N Nayan

Paul C Bornemann

Metal alloy injection molding techniques are described. In one or more implementations, these techniques may also include adjustment of injection pressure, configuration of runners, and/or use of vacuum pressure, and so on to encourage flow of the metal alloy through a mold. Techniques are also described that utilize protrusions to counteract thermal expansion and subsequent contraction of the metal alloy upon cooling. Further, techniques are described in which a radius of edges of a feature is configured to encourage flow and reduce voids. A variety of other techniques are also described herein.

Metal alloy injection molding

Metal alloy injection molding overflows

Metal alloy injection molding protrusions

Various methods of attaching a lid to an integrated circuit substrate are provided. In one aspect, a method of attaching a lid to a substrate that has an integrated circuit positioned thereon is provided. An adhesive is applied to the substrate and an indium film is applied to the integrated circuit. The lid is positioned on the adhesive. The adhesive is partially hardened and the indium film is reflowed. The adhesive is cured.

Lid attach process

Various semiconductor chips and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor wafer that has plural semiconductor chips. Each of the plural semiconductor chips includes a first principal side and a second and opposite principal side. Material is removed from the semiconductor wafer to define at least one rounded corner of the first principal side of at least one of the plural semiconductor chips.

Semiconductor chip with a rounded corner

Various sockets for packaged integrated circuits and methods of making the same are provided. In one aspect, a method of mounting a semiconductor chip is provided that includes providing a package that has a base substrate with a first side and a second side opposite the first side. The second side has a central region. The package includes a semiconductor chip and a lid coupled to the first side. A socket is provided for receiving the base substrate. The socket includes a mound that projects toward the second side of the base substrate when the base substrate is seated in the socket to provide support for the central region of the base substrate. The package is mounted in the socket. The mound provides support for the central region of the base substrate.

Integrated circuit socket

Various embodiments of a semiconductor chip device that include a circuit board and a stiffener frame and methods of fabricating the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a circuit board and coupling a stiffener frame to the circuit board. The stiffener frame includes a first opening that defines an interior wall. The interior wall includes a notch.

Circuit board with notched stiffener frame

Various methods and apparatus for holding a semiconductor chip package are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first plate adapted to hold a semiconductor chip package. The semiconductor chip package includes a carrier substrate and at least one semiconductor chip coupled to the carrier substrate. A second plate is formed with a first opening defining an interior peripheral surface adapted to compress an outer edge of the carrier substrate between the first plate and the second plate without engaging the at least one semiconductor chip.

Semiconductor chip package fixture

Thermal interface materials and method of using the same in packaging are provided. In one aspect, a thermal interface material is provided that includes an indium preform that has a first surface and a second surface opposite to the first surface, an interior portion and a peripheral boundary. The indium preform has a channel extending from the peripheral boundary towards the interior portion. The channel enables flux to liberate during thermal cycling.

Void reduction in indium thermal interface material

Apparatus and methods for assembling semiconductor chips packages are provided. In one aspect, a method of manufacturing is provided that includes placing a first set of semiconductor chip package substrates in a first group of receptacles of a first processing station. Each of the first set of semiconductor chip package substrates has a first footprint. The receptacles of the first group being dimensioned to accommodate the first footprint. A second set of semiconductor chip package substrates is placed in a second group of receptacles of the first processing station. Each of the second set of semiconductor chip package substrates has a second footprint larger than the first footprint. The receptacles of the second group being dimensioned to accommodate the second footprint. A first set of lids is placed on the first set of semiconductor chip package substrates and a second group of lids is placed on the second set of semiconductor chip package substrates.

Lid attachment mechanism

Various integrated circuit packages, lids therefor and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing an integrated circuit package lid that has a surface adapted to face towards an integrated circuit, and forming a wetting film on the surface. The wetting film has at least one void where the surface of the lid is exposed. The void inhibits bonding so that a stress reduction site is produced.

Integrated circuit package lid with a wetting film

Various method and apparatus for packaging an integrated circuit are provided. In one aspect, a method of packaging an integrated circuit is provided that includes coupling an integrated circuit to a substrate, mixing an adhesive with a plurality of particles, and coupling a lid to the substrate with the adhesive. At least a portion of the plurality of particles in the adhesive oppose compressive force from the lid to restrict rotation of the lid relative to the substrate.

Growing community of inventors

San Jose, CA, United States of America

Seah Sun Too