Samsung Electronics Co., Ltd.

Se Yong Oh

Yong Hwan Kwon

Sa Yoon Kang

Chan Eon Park

Sang Min Song

Shin Hyoung Kim

Young Jae Song

Tae Je Cho

Seung H Ahn

Hee-Guk Choi

Min Ho Lee

Se Ill Kim

A stacked chip package includes a substrate having an upper surface and a lower surface, a first semiconductor chip having an upper surface and a lower surface, wherein the lower surface of the first semiconductor chip is attached to the upper surface of the substrate and the upper surface of the first semiconductor chip includes a plurality of first electrode pads, and a second semiconductor chip having an upper surface and a lower surface. The lower surface of the second semiconductor chip is attached to the upper surface of the first semiconductor chip, and the lower surface of the second semiconductor chip includes trenches that correspond to the locations of the first electrode pads on the upper surface of the first semiconductor chip.

Stacked chip package having upper chip provided with trenches and method of manufacturing the same

Water-soluble polymeric adhesion promoter and production method

A method for manufacturing a chip scale package (CSP) including a semiconductor chip and conductive bumps is disclosed. In the present invention, a flexible substrate is provided with a conductive pattern formed thereon. The substrate has a top surface and a bottom surface. Then, a first photosensitive resin pattern is formed over the top surface of the substrate. Next, the first photosensitive resin pattern is cured. Subsequently, a second photosensitive resin pattern is formed over the cured first photosensitive resin pattern. The second photosensitive resin pattern includes a slit comprising a bottom of the first photosensitive resin pattern and side walls of the second photosensitive resin pattern. With the present invention, the problem of burning of neighboring patterns as well as the problem of the overflow of the encapsulant can be overcome.

Method for manufacturing a chip scale package having slits formed on a substrate

A lead-on-chip semiconductor device package is formed by attaching a lead frame having a single adhesive layer to a semiconductor chip. Electrode pads of the chip are electrically connected by bonding wires and mechanically connected by the adhesive layer to the lead frame, and then encapsulated by an encapsulant such as molding compound. The adhesive layer is formed from a liquid adhesive having a certain viscosity. The adhesive material is continuously applied to spaces between adjacent inner leads as well as the top surface of the leads and then cured. The leads are disposed at the same intervals and include some side leads with a larger width in order to form the adhesive layer with a uniform thickness. Thermoplastic resins are preferably used as the adhesive, but thermosetting resins may be used as well. In the case of thermoplastic resins, the temperature of a cure step is about 200.degree. C. and that of chip attachment step is about 400.degree. C.

Lead-on-chip semiconductor device package having an adhesive layer

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Seoul, South Korea

Se Yong Oh