Samsung Electronics Co., Ltd.

Se-Woong Park

Ki-Joon Kim

Kil-Ho Lee

Kilho Lee

Ki Joon Kim

Dong-Soo Chang

A semiconductor device and methods of forming a semiconductor device are disclosed. In the methods, a layer, such as an insulating interlayer, is formed on a substrate. A first trench is formed in the layer, and a mask layer is formed in the first trench. The mask layer has a first thickness from a bottom surface of the first trench to the top of the mask layer. The mask layer is patterned to form a mask that at least partially exposes a sidewall of the first trench. A portion of the mask adjacent to the exposed sidewall of the first trench has a second thickness smaller than the first thickness. The layer is etched to form a second trench using the mask as an etching mask. The second trench is in fluid communication with the first trench. A conductive pattern is formed in the first trench and the second trench.

Semiconductor structures having an insulative island structure

Semiconductor structures and methods of manufacturing the same

Nonvolatile memory devices and methods of fabricating the same, include, forming a transistor in a first region of a substrate, forming a contact which is connected to the transistor, forming an information storage portion, which is disposed two-dimensionally, in a second region of the substrate, sequentially forming a stop film and an interlayer insulating film which cover the contact and the information storage portion, forming a first trench, which exposes the stop film, on the contact, and forming a second trench which extends through the stop film to expose the contact, wherein a bottom surface of the first trench is lower than a bottom surface of the information storage portion.

Nonvolatile memory devices and methods of fabricating the same

Memory devices and methods of fabricating the same include a substrate including a cell region and a peripheral circuit region, data storages on the cell region, first bit lines on and coupled to the data storages, first contacts coupled to peripheral transistors on the peripheral circuit region, and second bit lines on and coupled to the first contacts. The second bit lines may each have a lowermost surface lower than a lowermost surface of the data storages.

Memory devices

Disclosed herein is a method of forming a nonvolatile memory device. The method comprises steps of forming a tunnel insulation pattern and a first floating gate pattern that are sequentially stacked on a semiconductor substrate, and then forming a trench comprising sidewalls aligned with the first floating gate pattern in the semiconductor substrate. Next, a device isolation layer is formed to fill in the trench, and an etch stop layer and a mold layer are sequentially formed on the device isolation layer and on the first floating gate pattern. The mold layer and the etch stop layer are successively patterned to form a groove exposing at least the first floating gate pattern, and a second floating gate pattern is formed to fill in the groove. This method can prevent bridges of floating gate layer that usually occur from regions not being fully etched due to high device integration.

Method of forming nonvolatile memory device

An apparatus and method of reducing impulse noise using a median filter involve selecting a pixel of median.sub.-- value from a plurality of pixels, comparing a reference range, determined by adding or subtracting an offset value to or from the selected median.sub.-- value, with a mid.sub.-- pixel among the plurality of pixels, to determine whether the input image signal has impulse noise and generate a noise coefficient depending on the presence of impulse noise, calculating a correlation between the luminance component of a pixel and the color component thereof depending on the noise coefficient, and cross-fading the pixel of median.sub.-- value and the mid.sub.-- pixel depending on the correlation.

Impulse noise reduction apparatus and method

A histogram equalization circuit includes a calculator and a mapper. The calculator calculates cumulative distribution function (CDF) values for the respective gray levels with respect to an input image corresponding to an area signal of a predetermined period. The mapper maps the input image of a predetermined period to a new gray level based on the CDF values of the respective gray levels. The present invention obtains a CDF value by selecting a field period or a frame period as a CDF calculation area and performs a histogram equalization the image signal of the selected period based on the CDF value. Calculation of the CDF is performed by direct comparison of the pixels of the image, thus eliminating the need to calculate a probability density function for the gray levels. Therefore, it is possible to obtain a high correlation between the input data and the equalized data and to reduce the quantity of hardware.

Video-image histogram equalization circuit and method therefor

A circuit and method for vertically expanding a display image in an image processing apparatus. The circuit includes a section for generating a signal for classifying a field of a color signal as an even field or an odd field; a multiplexer for multiplying lines of data output from a first memory and a second line memory by coefficients according to the signal for classifying the field as being an even field or an odd field; and a line of data output section for outputting a new line of data by adding the two lines of data corresponding to the lines of data output from a first memory and a second line memory.

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Seoul, South Korea

Se-Woong Park