Samsung Electronics Co., Ltd.

Samung Electronics Co., Ltd

Se-myeong Jang

Yong-chul Oh

Gyo-young Jin

Makoto Yoshida

Hyun-chang Kim

Nak-jin Son

Wook-Je Kim

Jae-Rok Kahng

Ki-nam Kim

Hong-sik Jeong

Hyo-dong Ban

Sang-hyun Han

Yoo-sang Hwang

A semiconductor device includes a substrate partitioned into a cell region, a peripheral circuit region, and an interface region between the cell region and the peripheral circuit region. A guard ring is provided in the interface region of the substrate and surrounds the cell region. A first gate structure is in the cell region, and a second gate structure is in the peripheral circuit region.

Semiconductor devices including guard ring structures

A semiconductor device is fabricating using a photoresist mask pattern, and selectively removing portions of a liner nitride layer in a cell region and a peripheral circuit region. A modified FinFET is formed to reduce the influence of signals transmitted by adjacent gate lines in a cell region. A double FinFET and a substantially planar MOSFET are formed in a core region and in a peripheral region, respectively, concurrently with the formation of the modified FinFET.

Method of fabricating FinFET devices

A method of manufacturing a local recess channel transistor in a semiconductor device. A hard mask layer is formed on a semiconductor substrate that exposes a portion of the substrate. The exposed portion of the substrate is etched using the hard mask layer as an etch mask to form a recess trench. A trench spacer is formed on the substrate along a portion of sidewalls of the recess trench. The substrate along a lower portion of the recess trench is exposed after the trench spacer is formed. The exposed portion of the substrate along the lower portion of the recess trench is doped with a channel impurity to form a local channel impurity doped region surrounding the lower portion of the recess trench. A portion of the local channel impurity doped region surrounding the lower portion of the recess trench is doped with a Vadjusting impurity to form a Vadjusting impurity doped region inside the local channel impurity doped region. The width of the lower portion of the recess trench is expanded. A gate insulating layer is formed on the substrate in the recess trench. A gate electrode layer is formed on the gate insulating layer in the recess trench. A portion of the gate insulating layer and the gate electrode layer is etched to form a gate.

Methods of manufacturing semiconductor devices with local recess channel transistors

Embodiments prevent or substantially reduce diffusion of a P-type impurity into a channel region in a PMOS transistor having a dual gate. Some embodiments include forming a device isolation film on a semiconductor substrate, forming a channel impurity region in an active region of the semiconductor substrate, and forming a gate insulation layer including a silicon oxide layer and a silicon oxide nitride layer on the semiconductor substrate. Also, the embodiments can include forming a polysilicon layer containing an N-type impurity on the gate insulation layer, and forming a gate electrode by selectively ion-implanting a P-type impurity into the polysilicon layer formed in a PMOS transistor region of the circuit region. The embodiments further include forming a conductive metal layer and a gate upper insulation layer on the gate electrode, and forming a gate stack in a gate region.

Method of doping polysilicon layer that utilizes gate insulation layer to prevent diffusion of ion implanted impurities into underlying semiconductor substrate

Integrated circuit devices are provided including an integrated circuit substrate and a gate on the integrated circuit substrate. The gate has sidewalls. A barrier layer spacer is provided on the sidewalls of the gate. A portion of the barrier layer spacer protrudes from the sidewalls of the gate exposing a lower surface of the barrier layer spacer that faces the integrated circuit substrate. A silicide layer is provided on the portion of the barrier layer spacer protruding from the sidewalls of the gate.

Integrated circuit devices having uniform silicide junctions

Semiconductor device and method of fabricating the same

Semiconductor devices with local recess channel transistors and methods of manufacturing the same

An integrated circuit device having a semiconductor substrate includes a gate structure on the semiconductor substrate. Source/drain regions are on opposite sides of the gate structure. A contact pad is on at least one of the source/drain region, and a silicide cap is on a surface of the contact pad opposite the respective source/drain region.

Semiconductor memory devices having contact pads with silicide caps thereon

Method of fabricating transistor of DRAM semiconductor device

Semiconductor memory devices having extending contact pads and related methods

A gate having sidewalls is formed on an integrated circuit substrate. A barrier layer spacer is formed on the sidewalls of the gate. A portion of the barrier layer spacer protrudes from the sidewalls of the gate exposing a lower surface of the barrier layer spacer that faces the integrated circuit substrate. A silicide layer is formed on the portion of the barrier layer spacer protruding from the sidewalls of the gate. Related devices are also provided.

Methods of fabricating integrated circuit devices having uniform silicide junctions

A semiconductor device including storage nodes of a capacitor and a method for manufacturing the same are provided. Bit lines are formed on a semiconductor substrate, and protection layers are formed to cover and protect the bit lines. Conductive contact pads are formed between the bit lines and are level with the top surfaces of the protection layers. A node supporting layer is formed to cover the conductive contact pads and the protection layers. An etching stopper is formed on the node supporting layer. The mold layer, the etching stopper, and the node supporting layer are patterned, thereby forming opening holes exposing the conductive pads. Storage nodes are formed in the opening holes and have the shape of the profile of the opening holes. The mold layer exposed by the storage nodes is removed, thereby exposing the outer wall of each of the storage nodes positioned above the etching stopper.

Method for manufacturing a semiconductor device including storage nodes of capacitor

A method for forming a lower electrode of a cylinder-shaped capacitor is provided to prevent etch skew and twin bit failure. The method includes sequentially forming a buffer layer and an etch stopper on a semiconductor substrate including a conductive region, forming a sacrificial dielectric layer on the etch stopper, forming a first opening within the sacrificial dielectric layer by etching a portion of the sacrificial dielectric layer using the etch stopper, depositing a slope-improving layer for improving sidewall slope of the first opening, forming a second opening by etching a portion of the slope-improving layer, the etch stopper and the buffer layer under the first opening and exposing the conductive region to which the cylinder-shaped capacitor is electrically connected, depositing a conductive layer for forming cylinder-shaped lower electrodes on a surface of the second opening, and forming the cylinder-shaped lower electrodes separated from each other.

Growing community of inventors

Gyeonggi-do, South Korea

Se-myeong Jang